Philips Semiconductors
Product specification
Quad 2-input NOR gate
74F02
FEATURE
•
Industrial temperature range available (–40°C to +85°C)
TYPE
TYPICAL
PROPAGATION
DELAY
3.4ns
TYPICAL SUPPLY
CURRENT
(TOTAL)
4.4mA
PIN CONFIGURATION
Q0
D0a
D0b
Q1
D1a
D1b
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Q3
D3b
D3a
Q2
D2a
D2b
74F02
SF00007
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F02N
N74F02D
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40°C to +85°C
I74F02N
I74F02D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
Dna, Dnb
Qn
Data inputs
Data output
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
50/33
LOAD VALUE HIGH/LOW
20µA/0.6mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC DIAGRAM
D0a
D0b
D1a
D1b
D2a
D2b
V
CC
= Pin 14
GND = Pin 7
D3a
D3b
2
3
5
6
8
9
11
12
13
1
Q0
FUNCTION TABLE
INPUTS
Dna
L
L
10
Q2
OUTPUT
Dnb
L
H
L
Qn
H
L
L
L
4
Q1
H
Q3
SF00008
H
H
NOTES:
1 H = High voltage level
2 L = Low voltage level
LOGIC SYMBOL
2
3
5
6
8
9
11 12
IEC/IEEE SYMBOL
2
3
1
1
D0a D0bD1a D1b D2a D2b D3a D3b
5
4
Q0 Q1 Q2 Q3
6
8
V
CC
= Pin 14
GND = Pin 7
1
4
10 13
10
9
SF00009
11
13
12
SF00010
1990 Oct 04
2
853-0326 00622
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74F02
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Commercial range
Industrial range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free air temperature range
Commercial range
Industrial range
0
–40
4.5
2.0
0.8
–18
–1
20
+70
+85
LIMITS
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
V
OH
V
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
High-level output voltage
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
Low-level output voltage
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
Ol
= MAX
Input clamp voltage
Input current at maximum input
voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)
4
I
CCH
I
CCL
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
V
CC
= MAX
-60
3.0
7.0
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
2.5
2.7
3.4
0.30
0.30
-0.73
0.50
0.50
-1.2
100
20
-0.6
-150
5.6
13.0
LIMITS
TYP
2
MAX
V
V
V
V
V
µA
µA
mA
mA
mA
mA
UNIT
NOTES:
1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2 All typical values are at V
CC
= 5V, T
amb
= 25°C.
3 Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4 I
CC
is measured with outputs open.
1990 Oct 04
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74F02
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
t
PLH
t
PHL
Propagation delay
Dna, Dnb to Qn
Waveform 1
2.5
2.0
TYP
4.4
3.2
MAX
5.5
4.3
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
2.5
2.0
MAX
6.5
5.3
V
CC
= +5.0V
±
10%
T
amb
= –40°C to +85°C
C
L
= 50pF, R
L
= 500Ω
MIN
2.5
1.5
MAX
7.0
6.0
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
Dna, Dnb
V
M
t
PHL
V
M
t
PLH
Qn
V
M
V
M
SF00005
Waveform 1. Propagation delay for inverting outputs
TEST CIRCUIT AND WAVEFORM
V
CC
NEGATIVE
PULSE
V
IN
PULSE
GENERATOR
R
T
D.U.T.
V
OUT
90%
V
M
10%
t
THL (
t
f
)
C
L
R
L
t
w
V
M
10%
t
TLH (
t
r
)
0V
90%
AMP (V)
t
TLH (
t
r
)
90%
POSITIVE
PULSE
V
M
10%
t
w
t
THL (
t
f
)
AMP (V)
90%
V
M
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude V
M
74F
3.0V
1.5V
rep. rate
1MHz
t
w
500ns
t
TLH
2.5ns
t
THL
2.5ns
SF00006
1990 Oct 04
4
stm32/stm8
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