FemtoClock® Crystal-to-HCSL
Clock Generator
Datasheet
841608
General Description
The 841608 is an optimized PCIe and sRIO clock generator. The
device uses a 25MHz parallel crystal to generate 100MHz and
125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (< 1ps rms) suitable to clock components requiring precise and
low-jitter PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the 841608 can also drive the
high-speed sRIO and PCIe SerDes clock inputs of communication
processors, DSPs, switches and bridges.
Features
•
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Eight HCSL outputs: configurable for PCIe (100MHz) and sRIO
(125MHz) clock signals
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input
Supports the following output frequencies: 100MHz or 125MHz
VCO: 500MHz
PLL bypass and output enable
PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.37ps (typical)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
XTAL_IN
1
Q0
Pin Assignment
REF_SEL
BYPASS
REF_IN
OSC
XTAL_OUT
REF_IN
Pulldown
REF_SEL
Pulldown
0
FSEL
IREF
GND
V
DDA
FemtoClock
PLL
1
VCO = 500MHz
nQ0
0
÷N
÷4
÷5
(default)
Q1
nQ1
Q2
XTAL_IN
XTAL_OUT
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
GND
Q2
nQ2
Q3
nQ3
V
DD
Q4
nQ4
V
DD
V
DD
nQ7
Q7
nQ6
Q6
GND
nQ5
Q5
M = ÷20
IREF
BYPASS
Pulldown
FSEL
Pulldown
MR/nOE
V
DD
Q0
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
nQ0
Q1
nQ1
841608
32-Lead VFQFN
5mm x 5mm x 0.925
mm package body
K Package
Top View
MR/nOE
Pulldown
©2016 Integrated Device Technology, Inc.
1
Revision B, May 4, 2016
841608 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1,
2
Name
XTAL_IN,
XTAL_OUT
Input
Type
Description
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance (Hi-Z).
When logic LOW, the internal dividers and the outputs are enabled.
Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3D.
Core supply pins.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Power supply ground.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Pulldown
Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B.
HCSL current reference resistor output. An external fixed precision resistor
(475
) from this pin to ground provides a reference current used for differential
current-mode Qx, nQx clock outputs.
Pulldown
Selects PLL operation/PLL bypass operation. Asynchronous function.
LVCMOS/LVTTL interface levels. See Table 3C.
Analog supply pin.
Pulldown
Pulldown
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3A.
LVCMOS/LVTTL PLL reference clock input.
3
MR/nOE
Input
Pulldown
4, 14, 24, 31
5, 6
7, 8
9, 19, 32
10, 11
12,13
15, 16
17, 18
20, 21
22, 23
25
26
V
DD
Q0, nQ0
Q1, nQ1
GND
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL
IREF
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Output
27
28
29
30
BYPASS
V
DDA
REF_SEL
REF_IN
Input
Power
Input
Input
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc.
2
Revision B, May 4, 2016
841608 Datasheet
Function Tables
Table 3A. REF_SEL Function Table
Input
REF_SEL
0
1
Input Reference
XTAL (default)
REF_IN
Table 3B. FSEL Function Table (f
REF
= 25MHz)
Inputs
FSEL
0
1
N Divider
5
4
Outputs
Q[0:7], nQ[0:7]
VCO/5 (100MHz) PCIe (default)
VCO/4 (125MHz) sRIO
Table 3C. BYPASS Function Table
Input
BYPASS
0
1
PLL Configuration
PLL enabled (default)
PLL bypassed (f
OUT
= f
REF
/N)
Table 3D. MR/nOE Function Table
Inputs
MR/nOE
0
1
Function
Outputs enabled (default)
Device reset, outputs disabled (high-impedance)
©2016 Integrated Device Technology, Inc.
3
Revision B, May 4, 2016
841608 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
37C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.15
Typical
3.3
3.3
Maximum
3.465
V
DD
87
15
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
REF_IN, REF_SEL,
BYPASS, FSEL,
MR/nOE
REF_IN, REF_SEL,
BYPASS, FSEL,
MR/nOE
V
DD
= V
IN
= 3.465V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
I
IL
Input Low Current
V
DD
= 3.465V, V
IN
= 0V
-5
µA
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
©2016 Integrated Device Technology, Inc.
4
Revision B, May 4, 2016
841608 Datasheet
AC Electrical Characteristics
Table 6B. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit(Ø)
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Phase Jitter Peak-to-Peak;
NOTE 2
Test Conditions
VCO/5
VCO/4
100MHz (1.875MHz – 20MHz)
125MHz (1.875MHz – 20MHz)
10
6
100MHz, (1.2MHz – 50MHz
Samples, 25MHz Crystal Input
Minimum
Typical
100
125
0.39
0.37
24.36
23.76
2.44
2.37
50
105
0.6
0.6
-100
4
4
100
1150
-300
250
550
140
48
500
90
52
Maximum
Units
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
V/ns
V/ns
mV
mV
mV
mV
mV
%
ps
ms
t
j
125MHz, (1.2MHz – 62.5MHz
10
6
Samples, 25MHz Crystal Input
100MHz, 10
6
Samples,
25MHz Crystal Input
125MHz, 10
6
Samples,
25MHz Crystal Input
t
REFCLK_HF_RMS
Phase Jitter RMS; NOTE 3
tjit(cc)
tsk(o)
Rise Edge Rate
Fall Edge Rate
V
RB
V
MAX
V
MIN
V
CROSS
V
CROSS
odc
t
STABLE
t
L
Cycle-to-Cycle Jitter; NOTE 4
Output Skew; NOTE 4, 5
Rising Edge Rate; NOTE 6, 7
Falling Edge Rate; NOTE 6, 7
Ringback Voltage; NOTE 6, 8
Absolute Maximum Output
Voltage; NOTE 9, 10
Absolute Minimum Output
Voltage; NOTE 9, 11
Absolute Crossing Voltage;
NOTE 9, 12, 13
Total Variation of V
CROSS
;
NOTE 9, 12, 14
Output Duty Cycle; NOTE 6, 15
Power-up Stable Clock Output;
NOTE 6, 8
PLL Lock Time
NOTE: All specifications are taken at 100MHz and 125MHz.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note,
PCI Express Reference Clock Requirements.
Maximum
limit for PCI Express is 86ps peak-to-peak.
NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz.
See IDT Application Note,
PCI Express Reference Clock Requirements.
Maximum limit for PCI Express Generation 2 is 3.1ps RMS.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 6: Measurement taken from a differential waveform.
NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
See Parameter Measurement Information Section.
NOTE 8: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 9: Measurement taken from a single-ended waveform.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
©2016 Integrated Device Technology, Inc.
5
Revision B, May 4, 2016
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