74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs
April 1993
Revised January 1999
74ABT16500
18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16500 18-bit universal bus transceiver combines
D-type latches and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. Output-enable OEAB is active-high.
When OEAB is HIGH, the outputs are active. When OEAB
is LOW, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
s
Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
s
Flow-through architecture optimizes PCB layout
s
Guaranteed latch-up protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
Ordering Code:
Order Number
74ABT16500CSSC
74ABT16500CMTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Connection Diagram
Pin Assignment for SSOP
Function Table
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
(Note 1)
Output
A
X
L
H
L
H
X
X
B
Z
L
H
L
H
B
0
(Note 2)
B
0
(Note 3)
Inputs
CLKAB
X
X
X
↓
↓
H
L
Note 1:
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2:
Output level before the indicated steady-state input conditions
were established.
Note 3:
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
© 1999 Fairchild Semiconductor Corporation
DS011581.prf
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74ABT16500
Logic Diagram
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2
74ABT16500
Absolute Maximum Ratings
(Note 4)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 5)
Input Current (Note 5)
Voltage Applied to Any Output
in the Disabled or
Power-off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to 5.5V
−0.5V
to V
CC
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500
mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 4:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 5:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
I
CCD
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
−100
−275
50
100
1.0
68
1.0
2.5
No Load
0.23
mA
µA
µA
mA
µA
mA
mA
mA/
MHz
Max
Max
0.0
Max
Max
Max
Max
Max
V
OUT
=
0V
V
OUT
=
V
CC
V
OUT
=
5.5V; All Others GND
All Outputs HIGH
An or Bn Outputs Low
OE
n
=
V
CC
,
All Others at V
CC
or GND
Additional I
CC
/Input
Dynamic I
CC
(Note 6)
Note 6:
Guaranteed, but not tested.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
Output Leakage Current
Min
2.0
Typ
Max
Units
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
0.8
−1.2
2.5
2.0
0.55
1
1
7
−1
−1
4.75
10
−10
V
V
V
V
V
µA
µA
µA
V
µA
µA
Min
Min
Min
Min
Max
Max
Max
0.0
I
IN
= −18
mA
I
OH
= −3
mA
I
OH
= −32
mA
I
OL
=
64 mA
V
IN
=
2.7V (Note 6)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V (Note 6)
V
IN
=
0.0V
I
ID
=
1.9
µA
All Other Pins Grounded
0
−
5.5V V
OUT
=
2.7V; OE, OE
=
2.0V
0
−
5.5V V
OUT
=
0.5V; OE, OE
=
2.0V
Output Leakage Current
V
I
=
V
CC
−
2.1V
All Others at V
CC
or GND
Outputs Open
Transparent Mode
One Bit Toggling, 50% Duty Cycle
3
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74ABT16500
DC Electrical Characteristics
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
−1.5
2.5
2.2
Min
Typ
0.7
−1.0
3.0
1.8
1.2
0.8
Max
1.2
Units
V
V
V
V
V
V
CC
5.0
5.0
5.0
5.0
5.0
Conditions
C
L
=
50 pF; R
L
=
500Ω
T
A
=
25°C (Note 7)
T
A
=
25°C (Note 7)
T
A
=
25°C (Note 8)
T
A
=
25°C (Note 9)
T
A
=
25°C (Note 9)
Note 7:
Max number of outputs defined as (n). n
−
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 8:
Max number of outputs defined as (n). n
−
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 9:
Max number of data inputs (n) switching. n
−
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock Frequency
Propagation Delay
A or B to B or A
Propagation Delay
LEAB or LEBA to B or A
Propagation Delay
CLKAB or CLKBA to B or A
Propagation Delay
OEAB or OEBA to B or A
Propagation Delay
OEAB or OEBA to B or A
150
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
V
CC
= +5V
C
L
=
50 pF
Typ
200
2.7
3.2
3.1
3.6
3.4
3.7
2.7
3.0
3.7
3.2
4.6
4.6
5.0
5.0
5.3
5.3
5.6
5.6
6.0
6.0
Max
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Min
150
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.6
4.6
5.0
5.0
5.3
5.3
5.6
5.6
6.0
6.0
ns
ns
ns
ns
Max
MHz
ns
Units
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74ABT16500
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(H)
t
W
(L)
Setup Time,
A to CLKAB
Hold Time,
A to CLKAB
Setup Time,
B to CLKBA
Hold Time,
B to CLKBA
Setup Time, A to LEAB
or B to LEBA, CLK HIGH
Hold Time, A to LEAB
or B to LEBA, CLK HIGH
Setup Time, A to LEAB
or B to LEBA, CLK LOW
Hold Time, A to LEAB
or B to LEBA, CLK LOW
Pulse Width,
LEAB or LEBA, HIGH
Pulse Width, CLKAB
or CLKBA, HIGH or LOW
4.5
4.5
0
0
4.0
4.0
0
0
1.5
1.5
1.5
1.5
4.5
4.5
1.5
1.5
3.3
3.3
3.3
3.3
V
CC
= +5V
C
L
=
50 pF
Max
Min
4.5
4.5
0
0
4.0
4.0
0
0
1.5
1.5
1.5
1.5
4.5
4.5
1.5
1.5
3.3
3.3
3.3
3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
50 pF
Max
ns
Units
Extended AC Electrical Characteristics
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
Symbol
Parameter
C
L
=
50 pF
18 Outputs Switching
(Note 10)
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable
Time
Propagation Delay
Data to Outputs
Propagation Delay
LEAB or LEBA to B or A
Propagation Delay
CLKAB or CLKBA to B or A
Output Enable Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Typ
Max
6.5
6.5
6.0
6.0
6.2
6.2
6.5
6.5
6.5
6.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
(Note 13)
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
250 pF
1 Output Switching
(Note 11)
Min
Max
7.0
7.0
7.5
7.5
7.7
7.7
7.0
7.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
(Note 13)
T
A
= −40°C
to
+85°C
V
CC
=
4.5V–5.5V
C
L
=
250 pF
18 Outputs Switching
(Note 12)
Min
Max
9.9
9.2
8.5
8.5
8.5
8.5
8.5
8.5
ns
ns
ns
ns
ns
Units
Note 10:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11:
This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 12:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 13:
3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet.
5
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