CY25403/CY25423/CY25483
Three PLL Programmable Clock Generator
with Spread Spectrum
Features
■
■
Three fully integrated phase-locked loops (PLLs)
Input frequency range
❐
External crystal: 8 to 48 MHz
❐
External reference: 8 to 166 MHz clock
Reference clock input voltage range
❐
1.8 V for CY25403/CY25423/CY25483
Wide operating output frequency range
❐
3 to 166 MHz
Programmable spread spectrum with center and down spread
option and lexmark and linear modulation profiles
V
DD
supply voltage options:
❐
2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483
Selectable output clock voltages independent of V
DD
supply:
❐
2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483
Frequency select feature with option to select four different
frequencies
Power-down, output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
Ability to synthesize nonstandard frequencies with Fractional-N
capability
■
■
■
■
Three clock outputs with programmable drive strength
Glitch-free outputs while frequency switching
8-pin SOIC package
Commercial and Industrial temperature ranges
■
Benefits
■
■
■
Multiple high performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable EMI reduction using Spread
Spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Suitability for PC, consumer, portable, and networking
applications
Capable of Zero PPM frequency synthesis error
Uninterrupted system operation during clock frequency switch
Application compatibility in standard and low power systems
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Block Diagram
XIN/
EXCLKIN
XOUT
OSC
PLL1
Crossbar
Switch
Output
Dividers
and
CLK1
(SS)
MUX
and
FS0
FS1
Control
Logic
PLL3
(SS)
SSON
PD#/OE
PLL 2
(SS)
Drive
Strength
Control
CLK2
(No SS)
CLK3
(SS)
Cypress Semiconductor Corporation
Document #: 001-12564 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 18, 2011
CY25403/CY25423/CY25483
Contents
General Description ......................................................... 4
Configurable PLLs ....................................................... 4
Input Reference Clocks ............................................... 4
VDD Power Supply Options ........................................ 4
Spread Spectrum Control ............................................ 4
Frequency Select ........................................................ 4
Glitch-Free Frequency Switch ..................................... 4
PD#/OE Mode ............................................................. 4
Output Drive Strength .................................................. 4
Generic Configuration and Custom Frequency ........... 4
Absolute Maximum Conditions ....................................... 5
DC Electrical Specifications ............................................ 6
AC Electrical Specifications ............................................ 7
Recommended Crystal Specification
for SMD Package .............................................................. 7
Recommended Crystal Specification
for Thru-Hole Package ..................................................... 8
Test and Measurement Setup .......................................... 8
Voltage and Timing Definitions ....................................... 8
Ordering Information ........................................................ 9
Possible Configurations ............................................... 9
Ordering Code Definitions ......................................... 10
Package Drawing and Dimensions ............................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Document #: 001-12564 Rev. *F
Page 2 of 14
CY25403/CY25423/CY25483
Table 1. Device Selector Guide
Device
CY25403/CY25423/CY25483 Yes
Crystal Input
EXCKLKIN Input
1.8 V LVCMOS
V
DD
2.5 V, 3.0 V, 3.3 V
Figure 1. Pin Diagram - CY25403/CY25423/CY25483 8-Pin SOIC
XIN/
EXCLKIN
V
DD
CLK1
CLK2/FS0
1
2
3
4
CY25403
8
7
6
5
XOUT
GND
CLK3/SSON
PD#/OE/FS1
Table 2. Pin Definition - CY25403/CY25423/CY25483 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
1
2
3
4
5
6
7
8
V
DD
CLK1
CLK2/FS0
PD#/OE/FS1
CLK3/SSON
GND
XOUT
Name
XIN/EXCLKIN Input
Power
Output
Output/Input
Input
Output/Input
Power
Output
IO
Power supply: 2.5 V, 3.0 V, or 3.3 V
Programmable clock output with spread spectrum
Multifunction programmable pin: programmable clock output with no spread spectrum
or frequency select pin
Multifunction programmable pin: power-down, output enable, or frequency select pin
Multifunction programmable pin: programmable clock output with spread spectrum or
spread spectrum ON/OFF control pin
Power supply ground
Crystal output
Description
Crystal input or 1.8 V external clock input
Document #: 001-12564 Rev. *F
Page 3 of 14
CY25403/CY25423/CY25483
General Description
Configurable PLLs
The CY25403/CY25423/CY25483 have three programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having three PLLs is that
a single device generates up to three independent frequencies
from a single crystal.
switched using output dividers. This feature enables
uninterrupted system operation while clock frequency is being
switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power-down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as output enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25403/CY25423/CY25483. The input frequency range for
crystal (XIN) is 8 MHz to 48 MHz and that for external reference
clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the
reference clock input CY25403/CY25423/CY25483 is 1.8 V. This
gives user an option for this device to be compatible for different
input clock voltage levels in the system.
V
DD
Power Supply Options
These devices have programmable power supply options. The
CY25403/CY25423/CY25483 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are four available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3.
Output clock source selection is done by using four out of four
crossbar switch. Thus, any one of these four available clock
sources can be arbitrarily selected for the clock outputs. This
gives user a flexibility to have up to three independent clock
outputs.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values.
Table 3
shows the typical rise
and fall times for different drive strength settings.
Table 3. Output Drive Strength
Output Drive Strength
Low
Mid Low
Mid High
High
Rise/Fall Time (ns)
(Typical Value)
6.8
3.4
2.0
1.0
Spread Spectrum Control
Two of the three PLLs (PLL2 and PLL3) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK3/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25403/CY25423/CY25483 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
Field Application Engineer (FAE) or sales
representative.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency
select inputs, can be used to select among these arbitrarily
programmed frequency settings. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
Document #: 001-12564 Rev. *F
Page 4 of 14
CY25403/CY25423/CY25483
Absolute Maximum Conditions
Parameter
V
DD
V
IN
T
S
ESD
HBM
UL-94
MSL
Description
Supply voltage for CY25403/CY25423/CY25483 –
Input voltage for CY25403/CY25423/CY25483
Temperature, Storage
ESD protection (human body model)
Flammability rating
Moisture sensitivity level
Relative to V
SS
Non Functional
JEDEC EIA/JESD22-A114-E
V-0 at 1/8 in.
SOIC package
Condition
Min
–0.5
–0.5
–65
2000
–
–3
10
Max
4.5
+150
Unit
V
°C
Volts
ppm
–
V
DD
+0.5 V
Recommended Operating Conditions
Parameter
V
DD
T
AC
T
AI
C
LOAD
t
PU
Commercial ambient temperature
Industrial ambient temperature
Maximum load capacitance
Power-up time for all V
DD
to reach minimum specified voltage
(power ramps must be monotonic)
Description
V
DD
operating voltage for CY25403/CY25423/CY25483
0
–40
–
0.05
Min
2.25
Typ
–
–
--
–
–
Max
3.60
+70
+85
15
500
Unit
V
°C
°C
pF
ms
Document #: 001-12564 Rev. *F
Page 5 of 14
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