Ethernet & USB Clock Generator for
Freescale B4/T4-based Systems
840NT4-01
DATA SHEET
General Description
The 840NT4-01 is clock generator designed to provide ethernet and
USB clocks for Freescale B4/ T4-based systems. The 840NT4-01
utilizes IDT’s FemtoClock NG
®
PLL technology to synthesize eight
low phase-jitter Ethernet reference clocks. The clock generator also
provides a 24MHz USB reference clock and a 25MHz reference
output.
Features
• Ten LVCMOS clock outputs:
Five LVCMOS 125MHz Ethernet outputs
Three LVCMOS 25MHz /125MHz Ethernet outputs
One LVCMOS 24MHz USB output
One LVCMOS 25MHz REF output
• QREF output can be used to drive other clock drivers, saving a
crystal
• Selectable crystal or differential LVPECL input
• RMS Phase Jitter, 125MHz, integration range 12kHz - 20MHz:
0.60ps (typical)
• Cycle-to-Cycle jitter: 20ps (typical)
• Flexible voltage supply modes; supports legacy and future system
requirements, minimizes power consumption
Core voltage: V
DD
, V
DD_XTAL
, V
DDA
Output voltage: V
DDO_A
, V
DDO_B
, V
DDO_C,
V
DDO_REF
Core / Output
3.3V / 3.3V
3.3V / 2.5V
3.3V / 1.8V
2.5V / 2.5V
2.5V / 1.8V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Recommended Application:
• Freescale B4/ T4 Ethernet /USB clock generator
Output Features:
• Five LVCMOS 125MHz Ethernet outputs
• Three LVCMOS 25MHz/ 125MHz Ethernet outputs
• One LVCMOS 24MHz USB output
• One LVCMOS 25MHz REF output
GND_QA
GND_QA
VDDO_A
VDDO_A
Table 1. Output Frequency Table
PD*
(MHz)
25
25
25
25
PLL_
SELA
0
0
0
0
PLL_
SELB
0
0
1
1
F
OUT
(MHz)
QA[4:0]
125
125
125
125
QB[2:0]
125
125
25
25
QC
24
24
24
24
QREF
25
25
25
25
Pin Assignment
OE_A
GND
GND
QA0
QA1
QA2
QA3
QA4
PSELB
0
1
0
1
VDD
PSELB
PLL_SELA
PLL_SELB
GNDA
VDDA
GND
VDD
RESERVED
VDD
XTAL_SEL
GND_XTAL
*PD = Phase Detector input frequency.
36 35 34 33 32 31 30
29 28 27 26 25
37
24
38
23
39
22
40
21
20
41
840NT4-01
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2
3
4 5 6 7
8
9 10 11 12
XTAL_OUT
PDIV_SEL
XTAL_IN
VDDO_REF
OE_REF
nPCLK
VDD_XTAL
GND_DSM
QREF
GND
PCLK
VDD
GND_QB
VDDO_B
QB0
QB1
QB2
VDDO_B
OE_B
VDDO_C
QC
GND_QC
OE_C
GND_REF
48-lead, 7.0mm x 7.0mm VFQFN
REVISION 2 05/18/15
1
©2015 Integrated Device Technology, Inc.
840NT4-01 DATA SHEET
Block Diagram
VDD
OE_REF
Pullup
VDDO_REF
25MHz
QREF
OE_A
OE_B
PLL_SELA
Pullup
Pullup
VDDO_A
Pullup
125MHz
Pulldown
XTAL_SEL
XTAL_IN
QA0
VDDA
25MHz
OSC
Femtoclock®NG
Pulldown
Pullup/
Pulldown
QA1
XTAL_OUT
PCLK
nPCLK
Phase Detector
VCO
÷M
QA2
5
PDIV_SEL
Pulldown
QA3
QA4
÷N1
VDDO_B
125MHz/
25MHz
QB0
÷N2
QB1
QB2
PSELB
PLL_SELB
OE_C
Pulldown
Pullup
Pullup
VDDO_C
÷NFRAC
24MHz
QC
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE
B4/T4-BASED SYSTEMS
2
REVISION 2 05/18/15
840NT4-01 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 2. Pin Descriptions
1
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
XTAL_IN
XTAL_OUT
V
DD_XTAL
PCLK
nPCLK
GND
V
DD
PDIV_SEL
GND_DSM
OE_REF
V
DDO_REF
QREF
GND_REF
OE_C
GND_QC
QC
V
DDO_C
OE_B
V
DDO_B
QB2
QB1
QB0
V
DDO_B
GND_QB
GND
GND_QA
QA4
QA3
QA2
V
DDO_A
V
DDO_A
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Input
Power
Input
Input
Power
Power
Input
Power
Input
Power
Output
Power
Input
Power
Output
Power
Input
Power
Output
Output
Output
Power
Power
Power
Power
Output
Output
Output
Power
Output power supply for Bank QAx clock outputs.
Power
Single-ended output clocks, optimized at 125MHz.
LVCMOS/LVTTL interface levels.
Output power supply for Bank QBx clock outputs.
Ground pin for Bank QBx clock outputs.
Power supply ground.
Ground pin for Bank QAx clock outputs.
Single-ended 125MHz or 25MHz clock outputs.
LVCMOS/LVTTL interface levels.
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pullup/
Pulldown
Power supply pin for XTAL.
Non-inverting external 25MHz differential LVPECL reference input.
LVPECL input levels.
Inverting external 25MHz differential LVPECL reference input.
LVPECL input levels.
Power supply ground.
Core supply pins.
Selects input for PCLK (LOW) or
5
pre-divider (HIGH).
LVCMOS/LVTTL interface levels.
Ground pin for Delta Sigma Modulator.
Output enable for QREF output. The output is placed in a high-impedance mode
on disable. LVCMOS/LVTTL interface levels.
Output power supply for QREF output.
Single-ended 25MHz, reference clock output. LVCMOS/LVTTL interface levels.
Ground pin for QREF clock output.
Output enable for QC output. The QC output is placed in a high-impedance
mode on disable. LVCMOS/LVTTL interface levels.
Ground pin for QC clock output.
Single-ended 24MHz, USB clock output. LVCMOS/LVTTL interface levels.
Output power supply for QC output.
Output enable for Bank QBx outputs. The output bank is placed in a
high-impedance mode on disable. LVCMOS/LVTTL interface levels.
Output power supply for Bank QBx clock outputs.
Type
Description
REVISION 2 05/18/15
3
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE
B4/T4-BASED SYSTEMS
840NT4-01 DATA SHEET
Table 2. Pin Descriptions
1
(Continued)
Number
32
33
34
35
36
37
38
39
Name
QA1
QA0
OE_A
GND_QA
GND
V
DD
PSELB
PLL_SELA
Output
Output
Input
Power
Power
Power
Input
Input
Pulldown
Pullup
Pullup
Type
Description
Single-ended output clocks, optimized at 125MHz.
LVCMOS/LVTTL interface levels.
Output enable for Bank QAx outputs. The output bank is placed in a
high-impedance mode on disable. LVCMOS/LVTTL interface levels.
Ground pin for Bank QAx clock outputs.
Power supply ground.
Core supply pins.
Select pin for Bank QBx first stage mux. Selects input for PLL enabled 25MHz
(LOW) or phase detector input frequency (HIGH). LVCMOS/LVTTL interface levels.
Bypasses the PLL for Bank A outputs. When LOW, selects PLL (PLL Enable).
When HIGH, bypasses the PLL. LVCMOS/LVTTL interface levels.
Select pin for Bank B second stage mux. Designed to operate with a phase
detector input frequency of 25MHz. The Bank B outputs generate 125MHz when
select pin is LOW and 25MHz when HIGH. LVCMOS/LVTTL interface levels.
Ground pin for PLL analog.
Analog supply pin.
Power supply ground.
Core supply pins.
Reserved pin. Do not connect.
Core supply pins.
Pulldown
Select input for XTAL (LOW) or PCLK pre-divider (HIGH).
LVCMOS/LVTTL interface levels.
Ground pin for XTAL.
40
41
42
43
44
45
46
47
48
PLL_SELB
GNDA
V
DDA
GND
V
DD
RESERVED
V
DD
XTAL_SEL
GND_XTAL
Input
Power
Power
Power
Power
Reserved
Power
Input
Power
Pullup
NOTE 1:
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 3. Pin Characteristics
1
Symbol
C
IN
Parameter
PDIV_SEL, OE_REF, OE_A,
Input
OE_B, OE_C, PLL_SELA,
Capacitance
PLL_SELB, PSELB, XTAL_SEL
Power Dissipation
Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
V
DDO_X
= 3.3V
R
OUT
Output Impedance
V
DDO_X
= 2.5V
V
DDO_X
= 1.8V
NOTE 1: V
DDO_X
denotes, V
DDO_A,
V
DDO_B,
V
DDO_C,
V
DDO_REF.
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE
B4/T4-BASED SYSTEMS
4
REVISION 2 05/18/15
V
DDO_X
= 3.465V
V
DDO_X
= 2.625V
V
DDO_X
= 1.89V
R
PULLUP
R
PULLDOWN
Test Conditions
Minimum
Typical
3.5
9
8
5
50
50
15
18
26
Maximum
Units
pF
pF
pF
pF
k
k
C
PD
840NT4-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Electrical Characteristicsis
not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Junction Temperature
Storage Temperature, T
STG
NOTE: V
DDO_X
denotes V
DDO_A
, V
DDO_B
, V
DDO_C
& V
DDO_REF.
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_X
+ 0.5V
125C
-65C to 150C
Rating
3.63V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DD_XTAL
= V
DDO_X
= 3.3V ± 5%, T
A
= -40°C to 85°C
1, 2
Symbol
V
DD
V
DD_XTAL
V
DDA
V
DDO_X
I
DD
+
I
DD_XTAL
I
DDA
I
DDO_X
Parameter
Core Supply Voltage
XTAL Power Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Outputs are Disabled to
High-Impedance
Test Conditions
Minimum
3.135
3.135
V
DD
– 0.06
3.135
Typical
3.3
3.3
3.3
3.3
Maximum
3.465
3.465
V
DD
3.465
150
30
8
Units
V
V
V
V
mA
mA
mA
NOTE 1: V
DDO_X
denotes, V
DDO_A
, V
DDO_B
, V
DDO_C
, V
DDO_REF.
NOTE 2: I
DDO_X
denotes, I
DDO_A
+ I
DDO_B
+ I
DDO_C
+ I
DDO_REF.
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DD_XTAL
= 3.3V ± 5%, V
DDO_X
= 2.5V ± 5%, T
A
= -40°C to 85°C
1, 2
Symbol
V
DD
V
DD_XTAL
V
DDA
V
DDO_X
I
DD
+
I
DD_XTAL
I
DDA
I
DDO_X
Parameter
Core Supply Voltage
XTAL Power Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Outputs are Disabled to
High-Impedance
Test Conditions
Minimum
3.135
3.135
V
DD
– 0.06
2.375
Typical
3.3
3.3
3.3
2.5
Maximum
3.465
3.465
V
DD
2.625
150
30
4
Units
V
V
V
V
mA
mA
mA
NOTE 1: V
DDO_X
denotes, V
DDO_A
, V
DDO_B
, V
DDO_C
, V
DDO_REF.
NOTE 2: I
DDO_X
denotes, I
DDO_A
+ I
DDO_B
+ I
DDO_C
+ I
DDO_REF.
REVISION 2 05/18/15
5
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE
B4/T4-BASED SYSTEMS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
