74F74 Dual D-Type Positive Edge-Triggered Flip-Flop
April 1988
Revised September 2000
74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The F74 is a dual D-type flip-flop with Direct Clear and Set
inputs and complementary (Q, Q) outputs. Information at
the input is transferred to the outputs on the positive edge
of the clock pulse. Clock triggering occurs at a voltage level
of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
Ordering Code:
Order Number
74F74SC
74F74SJ
74F74PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009469
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74F74
Unit Loading/Fan Out
U.L.
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
Description
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.8 mA
20
µ
A/
−
1.8 mA
−
1 mA/20 mA
Truth Table
Inputs
S
D
L
H
L
H
H
H
C
D
H
L
L
H
H
H
CP
X
X
D
X
X
X
h
l
X
Outputs
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
L
X
H (h)
=
HIGH Voltage Level
L (l)
=
LOW Voltage Level
X
=
Immaterial
Q
0
=
Previous Q (Q) before LOW-to-HIGH Clock Transition
Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F74
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
10.5
4.75
3.75
−0.6
−1.8
−150
16.0
5.0
7.0
50
µA
µA
µA
V
µA
mA
mA
mA
Max
Max
Max
0.0
0.0
Max
Max
Max
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (D, CP)
V
IN
=
0.5V (C
D
, S
D
)
V
OUT
=
0V
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
Min
Min
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
3
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74F74
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
100
3.8
4.4
3.2
3.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
125
5.3
6.2
4.6
7.0
6.8
8.0
6.1
9.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
100
3.8
4.4
3.2
3.5
7.8
9.2
7.1
10.5
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
D
n
to CP
n
Hold Time, HIGH or LOW
D
n
to CP
n
CP
n
Pulse Width
HIGH or LOW
C
Dn
or S
Dn
Pulse Width
LOW
Recovery Time
C
Dn
or S
Dn
to CP
2.0
3.0
1.0
1.0
4.0
5.0
4.0
2.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
2.0
3.0
1.0
1.0
4.0
5.0
4.0
2.0
ns
ns
Max
Units
ns
ns
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4
74F74
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
5
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