PD - 96138
IRFB4110QPbF
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
l
Lead-Free
Benefits
l
Improved Gate, Avalanche and Dynamic dv/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
175°C Operating Temperature
l
Automotive [Q101] Qualified
HEXFET
®
Power MOSFET
V
DSS
R
DS(on)
typ.
max
I
D
D
100V
3.7m
:
4.5m
:
180A
D
G
G
D
S
S
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
d
f
180
130
670
370
2.5
± 20
5.3
-55 to + 175
300
10lb in (1.1N m)
210
75
37
Units
A
W
W/°C
V
V/ns
°C
x
x
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Ã
e
g
Typ.
–––
0.50
–––
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
Junction-to-Case
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
k
Parameter
Max.
0.402
–––
62
Units
°C/W
j
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1
02/11/08
IRFB4110QPbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
––– –––
0.108 –––
3.7
4.5
–––
4.0
–––
20
––– 250
––– 100
––– -100
Conditions
V V
GS
= 0V, I
D
= 250µA
V/°C Reference to 25°C, I
D
= 5mA
mΩ V
GS
= 10V, I
D
= 75A
V V
DS
= V
GS
, I
D
= 250µA
µA V
DS
= 100V, V
GS
= 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
g
d
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
R
G
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
160
–––
–––
–––
–––
Conditions
V
DS
= 50V, I
D
= 75A
I
D
= 75A
V
DS
= 50V
V
GS
= 10V
–––
150
35
43
1.3
25
67
78
88
9620
670
250
820
950
–––
210
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Ω
g
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
i
–––
–––
–––
–––
–––
–––
–––
–––
–––
ns
pF
V
DD
= 65V
I
D
= 75A
R
G
= 2.6Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 80V
V
GS
= 0V, V
DS
= 0V to 80V
g
j
h
D
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Min. Typ. Max. Units
–––
–––
––– 170
–––
Conditions
MOSFET symbol
showing the
integral reverse
G
S
A
Ãdi
670
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
––– –––
1.3
V
–––
50
75
ns
–––
60
90
–––
94
140
nC
T
J
= 125°C
––– 140 210
–––
3.5
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
T
J
= 25°C
V
R
= 85V,
T
J
= 125°C
I
F
= 75A
di/dt = 100A/µs
T
J
= 25°C
g
g
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.074mH
R
G
= 25Ω, I
AS
= 75A, V
GS
=10V. Part not recommended for use
above this value.
I
SD
≤
75A, di/dt
≤
630A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
2
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IRFB4110QPbF
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
1000
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
BOTTOM
BOTTOM
4.5V
100
4.5V
100
≤
60µs PULSE WIDTH
Tj = 25°C
10
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
≤
60µs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
Fig 2.
Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
100
2.5
ID = 75A
VGS = 10V
2.0
10
T J = 175°C
1
T J = 25°C
1.5
VDS = 25V
≤60µs
PULSE WIDTH
0.1
1
2
3
4
5
6
7
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Fig 4.
Normalized On-Resistance vs. Temperature
12.0
ID= 75A
VGS, Gate-to-Source Voltage (V)
10.0
8.0
6.0
4.0
2.0
0.0
C, Capacitance (pF)
10000
Ciss
VDS= 80V
VDS= 50V
Coss
1000
Crss
100
1
10
VDS, Drain-to-Source Voltage (V)
100
0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4110QPbF
1000
10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
10
T J = 25°C
100µsec
100
10msec
1
VGS = 0V
0.1
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
10
Tc = 25°C
Tj = 175°C
Single Pulse
1
0
1
DC
1msec
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
180
160
140
ID, Drain Current (A)
Fig 8.
Maximum Safe Operating Area
125
Id = 5mA
120
115
110
105
100
95
90
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
Limited By Package
120
100
80
60
40
20
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
Fig 9.
Maximum Drain Current vs. Case Temperature
5.0
Fig 10.
Drain-to-Source Breakdown Voltage
900
EAS , Single Pulse Avalanche Energy (mJ)
4.5
4.0
3.5
800
700
600
500
400
300
200
100
0
ID
TOP
17A
26A
BOTTOM 75A
Energy (µJ)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
20
40
60
80
100
120
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (°C)
4
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
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IRFB4110QPbF
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
τ
J
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
R
3
R
3
τ
C
τ
1
τ
2
τ
3
τ
3
τ
C
Thermal Response ( Z thJC )
0.01
0.001
Ci=
τi/R
i
Ci=
τi/Ri
Ri (°C/W)
0.09876251
0.2066697
0.09510464
τ
i (sec)
0.000111
0.001743
0.012269
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
0.0001
1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
100
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-05
1.0E-04
1.0E-03
tav (sec)
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
250
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 75A
EAR , Avalanche Energy (mJ)
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
175
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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