NCP1217, NCP1217A
Enhanced PWM Current-Mode
Controller for High-Power
Universal Off-Line Supplies
Housed in an SO−8 or PDIP−7 package, the NCP1217 represents
the enhanced version of the NCP1203−based controllers. Due to its
high drive capability, NCP1217 drives large gate−charge MOSFETs,
which together with internal ramp compensation and built−in
overvoltage protection, ease the design of modern AC/DC adapters.
NCP1217 offers a true alternative to UC384X−based designs.
With an internal structure operating at different fixed frequencies
(65–100–133 kHz), the controller features a high−voltage startup FET,
which ensures a clean and loss less startup sequence. Its current−mode
control topology provides an excellent input audio−susceptibility and
inherent pulse−by−pulse control. Internal ramp compensation easily
prevents subharmonic oscillations from taking place in continuous
conduction mode designs.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1217 features two efficient protective circuitries: 1) In
presence of an overcurrent condition, the output pulses are disabled
and the device enters a safe burst mode, trying to restart. Once the
default has gone, the device auto−recovers. 2) If an external signal
(e.g. a temperature sensor) pulls Pin 1 above 3.2 V, output pulses are
immediately stopped and the NCP1217 stays latched in this position.
Reset occurs when the V
CC
collapses to ground, e.g. the user unplugs
the power supply.
Features
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MARKING
DIAGRAMS
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
XXXXX
ALYW
G
PDIP−7
P SUFFIX
CASE 626B
8
1
XXXXXX
A
L, WL
Y, YY
W, WW
G
or G
=
=
=
=
=
=
1
XXXXXXXXX
AWL
YYWWG
Specific Device Code
Assembly Location
Wafer Lot
Year
Work Week
Pb−Free Package
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current−Mode with Adjustable Skip−Cycle Capability
Built−in Internal Ramp Compensation
Auto−Recovery Internal Output Short−Circuit Protection
Internal 1.0 ms Soft−Start (NCP1217A Only)
Limited Duty−Cycle to 50% (NCP1217A Only)
Full Latchoff if Adjustment Pin is Brought High
Extremely Low No−Load Standby Power
Internal Temperature Shutdown
500 mA Peak Current Capability
Fixed Frequency Versions at 65 kHz, 100 kHz and 133 kHz
Direct Optocoupler Connection
Internal Leading Edge Blanking
SPICE Models Available for TRANsient and AC Analysis
These are Pb−Free Devices
High Power AC/DC Converters for TVs, Set−Top Boxes, etc.
Offline Adapters for Notebooks
Telecom DC−DC Converters
All Power Supplies
1
DEVICE MARKING INFORMATION
See detailed device marking information in the ordering
information section on page 17 of this data sheet.
PIN CONNECTIONS
Adj 1
FB 2
CS 3
GND
4
(Top View)
8
7
6
5
HV
NC
V
CC
Drv
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 17 of this data sheet.
Typical Applications
©
Semiconductor Components Industries, LLC, 2015
April, 2015
−
Rev. 9
Publication Order Number:
NCP1217/D
NCP1217, NCP1217A
See Application
Section
+
NCP1217
1
2
EMI
FILTER
UNIVERSAL
INPUT
3
4
Adj
FB
CS V
CC
Gnd Drv
HV
8
7
6
5
Aux.
+
V
OUT
Ramp Adjustment
+
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
1
Pin Name
Adj
Function
Adjust the skipping peak current
Description
This pin lets you adjust the level at which the cycle skipping process takes
place. Shorting this pin to ground permanently disables the skip cycle
feature.
By bringing this pin above 3.1 V, you permanently shut off the device.
By connecting an optocoupler to this pin, the peak current setpoint is ad-
justed accordingly to the output power demand.
This pin senses the primary current and routes it to the internal comparat-
or via an L.E.B. By inserting a resistor in series with the pin, you control
the amount of ramp compensation you need.
−
The driver’s output to an external MOSFET.
This pin is connected to an external bulk capacitor of typically 22
mF.
−
Ensures a clean and lossless
startup sequence
This unconnected pin ensures adequate creepage distance.
Connected to the high−voltage rail, this pin injects a constant current into
the V
CC
capacitor during the startup sequence.
2
3
FB
CS
Sets the peak current setpoint
Current sense input
4
5
6
7
8
GND
Drv
V
CC
NC
HV
The IC ground
Driving pulses
Supplies the IC
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2
NCP1217, NCP1217A
Latchoff
Comparator
Adj
1
+
−
80 k
+
-
HV
8
Set
Latch
HV Current
Source
3.1 V
Reset
UVLO
FB
2
1.1 V
+
-
Skip Cycle
Comparator
Internal V
CC
UVLO High and Low
NC
7
24 k
Current
Sense
3
250 ns
L.E.B.
19 k
Ramp
Compensation
20 k
Ground
4
+
−
V
REF
57 k
+
-
Drv
25 k
1V
1ms SS*
±500
mA
5
65−100−133 kHz
Clock
Set
Reset
Q Flip−Flop
DCmax = 74%
Reset
Q
V
CC
Overload
Management
6
* Available for “A” version only
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Power Supply Voltage
Power Supply Voltage on All Other Pins Except Pin 8 (HV), Pin 6 (V
CC
) and Pin 5 (Drv)
Maximum Voltage on Pin 8 (HV), Pin 6 (V
CC
) Decoupled to Ground with 10
mF
Maximum Voltage on Pin 8 (HV), Pin 6 (V
CC
) Grounded
Minimum Operating Voltage on Pin 8 (HV)
Maximum Current into All Pins Except V
CC
(6) and HV (8) when 10 V ESD Diodes are Activated
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Air, PDIP−7 Version
Thermal Resistance, Junction−to−Air, SO−8 Version
Maximum Junction Temperature
Temperature Shutdown
Hysteresis in Shutdown
Storage Temperature Range
ESD Capability, HBM Model (All Pins Except V
CC
and HV)
ESD Capability, Machine Model
−
R
qJC
R
qJA
R
qJA
T
JMAX
−
−
−
−
−
Symbol
V
CC
−
V
HV
V
HV
Value
16
−0.3
to 10
500
450
28
5.0
57
100
178
150
155
30
−60
to +150
2.0
200
Unit
V
V
V
V
V
mA
°C/W
°C/W
°C
°C
°C
°C
kV
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection rated using the following tests:
Human Body Model (HBM) 2000 V per JEDEC Standard JESD22, Method A114E.
Machine Model (MM) 200 V per JEDEC Standard JESD22, Method A115A.
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3
NCP1217, NCP1217A
V
CC
= 11 V unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
= 0°C to +125°C, Max T
J
= 150°C,
Characteristic
SUPPLY SECTION
(All frequency versions, unless otherwise noted)
Turn−On Threshold Level, V
CC
Going Up
Minimum Operating Voltage After Turn−On
V
CC
Decreasing Level at which the Latchoff Phase Ends
Internal IC Consumption, No Output Load on Pin 5,
F
SW
= 65 kHz
Internal IC Consumption, No Output Load on Pin 5,
F
SW
= 100 kHz
Internal IC Consumption, No Output Load on Pin 5,
F
SW
= 133 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
SW
= 65 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
SW
= 100 kHz
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
SW
= 133 kHz
Internal IC Consumption, Latchoff Phase, V
CC
= 6.0 V
INTERNAL STARTUP CURRENT SOURCE
(T
J
u
0°C)
High−Voltage Current Source, V
CC
= 10 V
High−Voltage Current Source, V
CC
= 0
DRIVE OUTPUT
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of a 12 V
Output Signal
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of a 12 V
Output Signal
Source Resistance
Sink Resistance
CURRENT COMPARATOR
(Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
Maximum Internal Current Setpoint
Default Internal Current Setpoint for Skip Cycle Operation
Propagation Delay from Current Detection to Gate OFF State
Leading Edge Blanking Duration
INTERNAL OSCILLATOR
(V
CC
= 11 V, Pin 5 Loaded by 1.0 kW)
Oscillation Frequency, 65 kHz Version
Oscillation Frequency, 100 kHz Version
Oscillation Frequency, 133 kHz Version
Maximum Duty−Cycle, NCP1217
Maximum Duty−Cycle, NCP1217A
−
−
−
−
−
f
OSC
f
OSC
f
OSC
Dmax
Dmax
58.5
90
120
69
42
65
100
133
74
46.5
71.5
110
146
80
50
kHz
kHz
kHz
%
%
3
3
3
3
3
I
IB
I
Limit
I
Lskip
T
DEL
T
LEB
−
0.9
−
−
−
0.02
1.0
330
90
250
−
1.1
−
150
−
mA
V
mV
ns
ns
5
5
5
5
T
r
T
f
R
OH
R
OL
−
−
15
5.0
60
20
20
10
−
−
35
18
ns
ns
W
W
8
8
IC1
IC2
3.5
(Note 2)
−
6.0
7.0
7.8
−
mA
mA
6
6
6
6
6
6
6
6
6
6
VCC
ON
VCC
min
VCC
latch
ICC1
ICC1
ICC1
ICC2
ICC2
ICC2
ICC3
11.8
6.9
−
−
−
−
−
−
−
−
12.8
7.6
5.6
960
1020
1060
1.7
2.1
2.4
230
13.8
8.3
−
1110
(Note 1)
1180
(Note 1)
1200
(Note 1)
2.0
(Note 1)
2.4
(Note 1)
2.9
(Note 1)
−
V
V
V
mA
mA
mA
mA
mA
mA
mA
Pin
Symbol
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Maximum Value @ T
J
= 0°C.
2. Minimum Value @ T
J
= 125°C.
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4
NCP1217, NCP1217A
ELECTRICAL CHARACTERISTICS
(continued)
(For typical values T
J
= 25°C, for min/max values T
J
= 0°C to +125°C,
Max T
J
= 150°C, V
CC
= 11 V unless otherwise noted.)
Characteristic
FEEDBACK SECTION
(V
CC
= 11 V, Pin 5 Loaded by 1.0 kW)
Internal Pull−Up Resistor
Pin 2 (FB) to Internal Current Setpoint Division Ratio
SKIP CYCLE GENERATION
Default Skip Mode Level
Pin 1 Internal Output Impedance
INTERNAL RAMP COMPENSATION
Internal Ramp Level @ 25°C (Note 3)
Internal Ramp Resistance to CS Pin
ADJUSTMENT LATCHOFF LEVEL
Latching Level
1
Vlatch
2.69
3.10
3.42
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. A 1.0 MW resistor is connected to the ground for the measurement.
3
3
Vramp
Rramp
2.6
−
2.9
19
3.2
−
V
kW
1
1
Vskip
Zout
0.93
−
1.1
27
1.26
−
V
kW
2
−
Rup
Iratio
−
−
19
3.3
−
−
kW
−
Pin
Symbol
Min
Typ
Max
Unit
TYPICAL CHARACTERISTICS
HV PIN LEAKAGE CURRENT @ 500V (mA)
80
70
60
VCC
OFF
, (V)
0
50
TEMPERATURE (°C)
150
50
40
30
20
10
0
−50
100
11.5
11.0
−50
13.0
12.5
12.0
14.0
13.5
0
50
TEMPERATURE (°C)
100
150
Figure 3. High Voltage Pin Leakage Current vs.
Temperature
9.0
3.0
2.8
8.5
VCC
MIN
, (V)
ICC 1.0 nF LOAD, (mA)
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
7.0
−50
0
50
TEMPERATURE (°C)
100
150
1.0
−50
Figure 4. VCC
OFF
vs. Temperature
133 kHz
100 kHz
8.0
7.5
65 kHz
0
50
TEMPERATURE (°C)
100
150
Figure 5. VCC
MIN
vs. Temperature
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5
Figure 6. ICC 1.0 nF Load vs. Temperature
FPGA/CPLD
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