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74VHC02FTBJ

产品描述USB Interface IC USB 2.0 PHY ULPI
产品类别半导体    逻辑   
文件大小154KB,共8页
制造商Toshiba(东芝)
官网地址http://toshiba-semicon-storage.com/
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74VHC02FTBJ概述

USB Interface IC USB 2.0 PHY ULPI

74VHC02FTBJ规格参数

参数名称属性值
产品种类
Product Category
Logic Gates
制造商
Manufacturer
Toshiba(东芝)
RoHSDetails
产品
Product
Single-Function Gate
Logic FunctionNOR
Logic Family74VHC
Number of Gates4 Gate
Number of Input Lines8 Input
Number of Output Lines4 Output
High Level Output Current- 8 mA
Low Level Output Current8 mA
传播延迟时间
Propagation Delay Time
5.1 ns at 5 V
电源电压-最大
Supply Voltage - Max
5.5 V
电源电压-最小
Supply Voltage - Min
2 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
TSSOP-14
系列
Packaging
Reel
系列
Packaging
MouseReel
系列
Packaging
Cut Tape
工作温度范围
Operating Temperature Range
- 40 C to + 85 C
Output Current25 mA
Output Voltage0 V to 5.5 V
Pd-功率耗散
Pd - Power Dissipation
180 mW
工厂包装数量
Factory Pack Quantity
2500
单位重量
Unit Weight
0.004949 oz

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74VHC02FT
CMOS Digital Integrated Circuits
Silicon Monolithic
74VHC02FT
1. Functional Description
Quad 2-Input NOR Gate
2. General
The 74VHC02FT is an advanced high speed CMOS 2-INPUT NOR GATE fabricated with silicon gate C
2
MOS
technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and
stable output.
An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature: T
opr
= -40 to 125
High speed: Propagation delay time = 3.6 ns (typ.) at V
CC
= 5.0 V
Low power dissipation: I
CC
= 2.0
µA
(max) at T
a
= 25
High noise immunity: V
NIH
= V
NIL
= 28 % V
CC
(min)
Power-down protection is provided on all inputs.
Balanced propagation delays: t
PLH
t
PHL
Wide operating voltage range: V
CC(opr)
= 2.0 to 5.5 V
Low noise: V
OLP
= 0.8 V (max)
(10) Pin and function compatible with the 74 series (AC/HC/AHC/LV etc.) 02 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4. Packaging
TSSOP14B
Start of commercial production
©2016 Toshiba Corporation
1
2013-11
2016-07-07
Rev.5.0

 
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