CY28445-5
Clock Generator for Intel
®
Calistoga Chipset
Features
• Compliant to Intel
®
CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#
• 96/100 MHz Spreadable differential video clock.
CPU
x2 / x3
SRC
x8/9/10
PCI
x7
REF
x2
DOT96
x1
USB_48M
x1
LCD100M
x1
27M
x2
• 33 MHz PCI clock
• Buffered 14.318 MHz Reference Clock
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 68-pin QFN (MLF) package
Block Diagram
XIN
XOUT
SEL_CLKREQ
PCI_STP#
CPU_STP#
CLKREQ
#
ITP_SEL
FS[C:A]
14.318M
Hz
Crystal
PLL Reference
VDD
REF
IREF
VDD
CPUT[0:1]
CPUC[0:1]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
SRCT[1:8]
SRCC[1:8]
VDD
PCI[1:5]
VDD_PCI
PCIF[0:1]
VDD
LVDS
PLL
FCTSEL[0:1]
27M
Hz
PLL
Fixed
PLL
I2C
Logic
Pin Configuration
PCIF0 / ITP_SEL
VDD_PCI
VSS_PCI
PCI5 / FCTSEL1
PCI4
PCI3
VSS_PCI
VDD_PCI
CLKREQ#_5
CLKREQ#_3
PCI2
PCI1
PCI_STP#
CPU_STP#
REF0 / FSC
REF1 / FCTSEL0
VSS_REF
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
PCIF1
VTT_PWRGD# / PD
VDD48
48M/FSA
VSS48
DOT96T / 27MHz non spread
DOT96C/ 27MHz spread
FSB
CLKREQ#_1
SRCT_0 / LCD100MT
SRCC_0 / LCD100MC
VDD_SRC
SRCT_1
SRCC_1
SRCT_2
SRCC_2
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP / SRCT_10
CPUC2_ITP / SRCC_10
VDD_SRC
CPU
PLL
Divider
CY28445-5
Divider
SRCT0/100M
T_SST
SRCC0/100M
C_SST
VDD
27M- Spread
Divider
Divider
VDD48
27M non Spread
-
VDD48
DO
T96T
DO
T96C
VDD48
48M
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SRCT_3
SRCC_3
CLKREQ#_4
SRCT_4
SRCC_4
SRCT_5
SRCC_5
CLKREQ#_6
SRCT_6
SRCC_6
VDD_SRC
SRCT_7
SRCC_7
VSS_SRC
SRCC_8
SRCT_8
CLKREQ#_8
VTT_PW D#/PD
RG
SDATA
SCLK
........................Document #: 38-07739 Rev *C Page 1 of 25
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY28445-5
Pin Descriptions
Pin No.
1
2
PCIF1
VTT_PWRGD#/PD
Name
Type
O, SE
33 MHz clock output
I, PD
3.3V LVTTL input.
This pin is a level sensitive strobe used to latch the FS[C:A],
ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW)
assertion, this pin becomes a real-time input for asserting power-down (active
HIGH).
3.3V power supply.
3.3V-tolerant input for CPU frequency selection / Fixed 48 MHz clock output.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications.
Ground.
Description
3
4
5
6, 7
VDD48
FSA/48M
VSS48
PWR
I/O
GND
O, DIF
Fixed 96 MHz differential clock output / Single ended 27 MHz clock outputs.
DOT96T/27M_non
When configured for 27 MHz, only the clock on pin 7contains spread.
spread
Selected via FCTSEL[0:1] at VTT_PWRGD# assertion.
DOT96C/27M_Spread
FSB
I
I, PU
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications
3.3V LVTTL input for enabling assigned SRC clock (active LOW)
8
9, 20, 25, 34, CLKREQ#[1], [3:6], [8]
59, 60
10, 11
SRC[T/C]0/
LCD100M[T/C]
O,DIF
100 MHz differential serial reference clock output / 100 MHz LVDS differ-
ential clock output.
Selected via FCTSEL[0:1] at VTT_PWRGD# assertion
PWR
3.3V power supply
O, DIF
100 MHz differential serial reference clock outputs.
12, 17, 28, 35 VDD_SRC
13,14, 15,
16, 18, 19,
21, 22, 23,
24, 26, 27,
29, 30, 32,
33,
31
36, 37
SRC[T/C][1:8]
VSS_SRC
GND
Ground.
CPUT2_ITP/SRCT10, O, DIF
Selectable differential CPU / SRC clock output.
CPUC2_ITP/SRCC10
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC10 (default)
ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP
VDDA
VSSA
IREF
PWR
GND
I
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin,
which is connected to the internal
current reference.
3.3V power supply
Ground
SMBus-compatible SCLOCK.
3.3V power supply
14.318 MHz crystal input.
38
39
40
41, 42, 44, 45 CPU[T/C][0:1]
43
46
47
48
49
50
51
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
O, DIF
Differential CPU clock outputs.
PWR
GND
I
PWR
I
I/O, OD
SMBus-compatible SDATA.
O, SE
14.318 MHz crystal output.
....................... Document #: 38-07739 Rev *C Page 2 of 25
CY28445-5
Pin Descriptions
(continued)
Pin No.
53
Name
REF1/FCTSEL0
Type
Description
I/O, SE
Fixed 14.318 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7
PD
(DOT96[T/C], 27M-non-spread and Spread) and pin 10,11 (SRC[T/C]0 or
100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 FCTSEL0 PIN 6
0
0
1
1
0
1
0
1
DOT96T
DOT96T
OFF Low
PIN 7
DOT96C
DOT96C
TBD
PIN 10
SRCT0
SRCT0
PIN 11
SRCC0
SRCC0
SRCC0
100MT_SST 100MC_SST
27M_non spread 27M_Spread SRCT0
54
REF0/FSC
I/O
Fixed 14.318 MHz clock output / 3.3V-tolerant input for CPU frequency
selection.
Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C
specifications
3.3V LVTTL input for CPU_STP# active LOW.
3.3V LVTTL input for PCI_STP# active LOW.
3.3V power supply
Ground
55
56
61, 67
62, 66
65
CPU_STP#
PCI_STP#
VDD_PCI
VSS_PCI
PCI5/FCTSEL1
I, PU
I, PU
PWR
GND
57, 58, 63, 64 PCI[1:4]
O, SE
33 MHz clock outputs.
O, SE
33 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7
PD
(DOT96[T/C], 27M-non-spread and Spread) and pin10,11 (SRC[T/C]0 or
100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 FCTSEL0 PIN 6
0
0
1
1
0
1
0
1
DOT96T
DOT96T
OFF Low
PIN 7
DOT96C
DOT96C
TBD
PIN 10
SRCT0
SRCT0
PIN 11
SRCC0
SRCC0
SRCC0
100MT_SST 100MC_SST
27M_non spread 27M_Spread SRCT0
68
PCIF0/ITP_SEL
I/O, SE
33 MHz clock output / 3.3V LVTTL input to enable SRC[T/C]10 or
CPU[T/C]2_ITP on pin 36, 37.
(sampled on the VTT_PWRGD# assertion).
0 = SRC10 (default)
1 = CPU2_ITP,
Table 1. Frequency Select Table FSA, FSB and FSC
FSC
1
0
0
0
FSB
0
0
1
1
FSA
1
1
1
0
CPU
100 MHz
133 MHz
166 MHz
200 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
....................... Document #: 38-07739 Rev *C Page 3 of 25
CY28445-5
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
Table 2. Command Code Definition
Bit
7
(6:0)
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
....................... Document #: 38-07739 Rev *C Page 4 of 25
CY28445-5
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
/LCD100M[T/C]
Description
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0 /LCD100M[T/C] Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
7
6
5
4
3
@Pup
1
1
1
1
1
PCIF0
27M_nss / DOT_96[T/C]
USB_48MHz
REF0
REF1
Name
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
27M_nss and DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
Description
....................... Document #: 38-07739 Rev *C Page 5 of 25
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