MAX9530
Quad NTSC/PAL Decoder and Quad Audio Codec
_____________
General Description
The MAX9530 is a quad-channel video decoder and
audio codec for security & surveillance applications. The
part is specially designed to serve as the front-end in
multi-channel DVR (Digital Video Recorder) and DVS
(Digital Video Streamer) systems. The architecture
supports byte- or frame-interleaved digital video output
for direct connection to a wide selection of multi-channel
A/V media processors including Maxim’s own H.264
codec family (i.e. MG3500 and later generations). The
on-chip DDR2 memory controller enables output of
frame-synchronized digital video from up to four
asynchronous analog video inputs. Multiple devices can
be configured to support an unlimited number of
synchronized video streams. The use of external
memory is optional. A memory bypass mode provides
for output of up to four-channels of asynchronous video
data in BT.656 digital component format.
The video signal path produces excellent video quality
derived from four 54MHz/10-bit ADCs and a 5L comb
filter bank. Differential or single-ended video and audio
inputs are supported. The video input path includes a DC
restore circuit, analog gain control, and anti-aliasing filter for
each channel with no additional external components. Long
cable connections are supported with the use of an adaptive
equalizer block that automatically adjusts and compensates for
high-frequency video signal losses in each channel
independently. Each video channel can also be downscaled in
high-quality for recording in lower resolution formats. All video
capture operates from a unique “PLL-less” design, to ensure
instant lock, and no loss of video content waiting for lock to
occur with the incoming video.
In addition, four mono audio channels are captured in
16-bit precision with programmable sample rates from
16 to 48kHz. Three independent I2S interfaces provide
digital audio input/output for record, playback, and
mixing operations. A separate inter-chip Audio Link bus
allows cascaded operation for multi-channel systems
with 8/16/etc. channel inputs. Two analog audio outputs
are also provided.
The digital I/Os can operate from 1.7 to 3.6V.
______________________
Features
Video Features:
4-ch Analog Video Decoder – NTSC (M,J,4.43) or
PAL(B,G,H,I,D,N,M,60)
4-ch Frame-Interleaved Output Synchronizer
(optional with external DDR2 memory).
Programmable 2D Video Scalers
Independent Auto Cable EQ per Video Channel
Instant Lock System for Video Capture
Multi-Line Adaptive Comb Filters.
4x Oversampled 54MHz/10-bit Video ADC
Output formats –
Video - 4x8-bit non-interleaved or 2x2x8-bit /
1x4x8-bit interleaved
DVR Multiplex Output:
With DDR2 – Pixel or Frame Interleaved
Without DDR2 – BT.656 Pixel Multiplex
Audio Features:
4-ch Analog Audio Input (Mono)
48KHz/16 bit Audio ADC.
2-ch Analog Audio Output
Differential or Single-Ended Analog Inputs
2
I C Interface
1400mW Typical Power Dissipation (w. DDR)
1.8V Analog Supply Voltage
1.8V Digital Core Supply Voltage
1.8V to 3.3V Digital I/O Voltage
JTAG Support
____________Ordering
Information
PART
INPUTS
PIN-PACKAGE
MAX9530CXV+
4+ 4
CSBGA 196
All devices specified over the 0ºC to +70ºC
operating temperature range.
+ Denotes lead(Pb)-free/RoHS-compliant package.
___________________Applications
Security Surveillance/CCTV Systems
Digital Video Recorders (DVRs)
Digital Video Streamers (IP Streaming)
Page 1 of 83
1. BLOCK DIAGRAM
MAX9530 Functional Block Diagram
DDR 2 DA TA I /O
DDR2 MEMORY Controller
Frame Sync
Video Multiplexer
Video1
Video2
Video3
Video4
ITU 656 Output 1 or 1&2 @ 54MHz
ITU 656Output 2
ITU 656 Output 3 or 3&4 @ 54MHz
ITU 656 Output 4 or 1 & 2 & 4 @ 108MHz
Vout 1 [7: 0]
Vout 2 [7: 0]
Vout 3 [7: 0]
Vout 4 [7: 0]
DDR2 Memory Connections
LLC
LLCB
Video Timing
Interface
TPP1
TPP2
TPP3
TPP4
AMCLK
BCLKR
LRCLKR
SDOUT
SDOUTM
BCLKP
LRCLKP
SDIN
ALINKI
ALINKO
Audio & Video Input
Video 1
PREG
PREF
Analog
LPF
Analog:
AGC, Clamp, LPF
ADC
10b
Auto
Cable
EQ
CH1
CVBS
Decoder
10 bit
HV Sc alar
Rec. Ch
ADC
16
b
Audio 1
Decimation Filter
P.back Ch.
I 2S
Interface
Video 2
Audio 2
CH2
A/V Router
P.Back Ch[1 of 5]
Audio analog
output 1Ch .
Audio 5 ch. Mixer
and analog
output
Audio Out 1
Video 3
Audio 3
P Back Ch[5]
.
CH3
Audio Out 1
27/108 MHz
Ext Clock
Video 4
Audio 4
I2C IF
SDA
SCL
DEVADDR
IRQB
CH4
Clock
Generator
and Timing
27MHz
Href
Fref
I2C CPU Interface
Figure 1: MAX9530 Block Diagram
2. TABLE OF CONTENTS
3. ABSOLUTE MAXIMUM RATINGS
Supply Voltages
VDDA to GND ...................................................................................................................... -0.3V to +2V
VDDD to GND....................................................................................................................... -0.3V to +2V
VDDIO to GND ..................................................................................................................-0.3V to +3.6V
Outputs
VOUT_<7:0>, PCLK_, TPP_ ............................................................................... -0.3V to (VDDIO+0.3V)
AOUT_…........................................................................................................... -0.3V to (VDDA+0.3V)
PREG, REF, VCM…….......................................................................................... -0.3V to (VDDA+0.3V)
IRQB, SDA, TDO ............................................................................................................... -0.3V to +3.6V
Inputs
VIN_, AIN_............................................................................................................ -0.3V to (VDDA+0.3V)
XTAL1, XTAL2...................................................................................................... -0.3V to (VDDA+0.3V)
SDIN ………………………………………….…………………………………………-0.3V to (VDDIO+0.3V)
SDA, SCL, DEVADDR<1:0>, TMS, TDI, TCK, JTAG_RST .............................................. -0.3V to +3.6V
Input/Outputs
LRCLK_, BCLK_, SDOUT……………………………………............................ -0.3V to (VDDIO+0.3V)
A<12:0>, DQ<15:0>, _DQS, RASB,
CASB, WEB, CSB, _DM, CKE, CK_, ODT ................................................................ -0.3V to (VDDD+0.3V)
Continuous Current
Page 2 of 83
All Pins........................................................................................................................................ +/-50mA
Continuous Power Dissipation (TA = +70ºC) 196 pin CSBGA Multilayer Board
(derate 20.8mW/C above +70C) …………………………………………………………………………1860mW
Operating Temperature Range ................................................................................................. 0ºC to +70ºC
Junction Temperature ........................................................................................................................ +150ºC
Storage Temperature Range ................................................................................................-65ºC to +150ºC
Lead Temperature (soldering, 10sec)................................................................................................. +260ºC
Note A:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations see
www.maxim-ic.com/thermal-tutorial
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4. ELECTRICAL CHARACTERISTICS: EC TABLE
(VDDA = VDDD = +1.8V, VDDIO = +3.3V, GND = 0V, T
A
= 0°C to 70°C, unless otherwise noted. Typical
values are at T
A
= +25°C.) (Note 1)
PARAMETER
SUPPLIES
Analog Supply Voltage Range
Digital Supply Voltage Range
Digital I/O Supply Voltage Range
Analog Supply Current
Digital Supply Current
Digital I/O Supply Current
I
VDDIO
SYMBOL
CONDITIONS
MIN
VDDA
VDDD
VDDIO
I
VDDA
I
VDDD
Normal Operation (Note 2)
Shutdown (XTAL=0Hz)
Normal Operation (Note 2)
Shutdown (XTAL=0Hz)
Normal Operation (Note 2). VDDIO=1.8V
Normal Operation (Note 2). VDDIO=3.3V
Shutdown. DVDD_IO=3.3V (T
A
= 25°C)
ANALOG VIDEO INPUT
Video Input Reference (VREF)
V
REF
Video Input Resistance
R
IN
Video Input Capacitance
C
IN
Diff. Video Input CMRR
CMRRv
Video Sync Level Adjust
(Source and Sink Values)
(Note 6)
DC Restore Current DAC Full Scale
Range (Source and Sink)
ANALOG INPUT FILTER AND ADC (Note 4)
Video Passband Cutoff (3dB)
F
3dB
Video Passband Flatness
Video Stopband Cutoff
Video Stopband Attenuation
F
SB
f > F
SB
, V
AIN
= 0.65V
P-P
reference level is measured at 1MHz
1.7
1.7
1.7
EC Table
TYP
1.8
1.8
3.3
152
2
344
50
52
150
10
775
2
8
80
3
6
12
24
13
f < F
PB
, V
AIN
= 0.65V
P-P
reference level is measured at 1MHz
0.25
53
36
UNITS
MAX
1.9
1.9
3.45
250
200
490
1000
V
V
V
mA
µA
mA
µA
mA
mA
µA
mV
MΩ
pF
dBFS
3.9
7.8
16
32
MHz
dB
MHz
dB
µA
Freq. range 0
5MHz
Slow
Medium
Medium-Fast (default)
Fast
2.1
4.2
8
16.4
Page 3 of 83
PARAMETER
SYMBOL
CONDITIONS
MIN
AGC Disabled, Gain
Programmed
via I
2
C,Referenced to VINxN,
Gain Error=5%
ADCGAIN=0x0
680
EC Table
TYP
UNITS
MAX
840
mV
pp
Video Full-Scale Conversion
Single End Input
ADCGAIN=0xF
280
1370
550
0.150
54
10
±0.5
±1
340
1690
670
mV
pp
mV
pp
mV
pp
V/V
MHz
Bits
LSB
LSB
dB
dBFS
Video Full-Scale Conversion
Differential Input
ADCGAIN=0x0
AGC Disabled,
Gain Programmed
via I
2
C, Referenced to VINxN,
Gain Error=5%
ADCGAIN=0xF
Fadc
ADCR
DNL
INL
SNR
PSRV
DP
DG
Luminance Flat Field -50% gray
Av=0000,
1.7V<V
VDDA
<1.9V
ADCGAIN[3:0]=0x0
1.7V<V
VDDD
<1.9V
T
A
= +25°C
1.7V<V
VDDIO
<3.45V
5 step Modulated Staircase,
f =3.58MHz or 4.43MHz
5 step Modulated Staircase,
f =3.58MHz or 4.43MHz
2T = 200ns
2T = 250ns
Between video channels
Between audio input channels
Video AGC Step Size
ADC Clock Rate
ADC Resolution
Video DC differential nonlinearity
Video DC integral nonlinearity
Video Signal-to-RMS noise ratio
(Includes filter + ADC + digital anti-aliasing
filter)
Video Power Supply Rejection
Video Differential Phase
Video Differential Gain
Video 2T Pulse Response
Crosstalk
56
33
1.0
1
0.2
70
90
1.0
5.5
1.0
1
+/- 1
1.5
8
12
18
400
Deg.
%
K%
dB
MHz
MHz
%
%
deg
%
µs
dB
ps
p-p
MHz
pF
pF
ppm
ps
pp
400
kHz
µs
DECODED LUMINANCE and CHROMINANCE
Video Chrominance Bandwidth
BW
C
Video Luminance Bandwidth
BW
L
Video Luminance Non-Linearity
Chroma Amplitude error
Chroma Phase Error
Video Horizontal Line Time Static Variation
Video Maximum Horizontal Line Time Jitter
Video Input Signal
Minimum Peak Signal to RMS Noise
CLOCK GENERATOR
Video Clock Jitter
CRYSTAL OSCILLATOR (XTAL1, XTAL2)
Frequency
C
XTAL1
,
XTAL1, XTAL2 Input Capacitance
C
XTAL2
Maximum Load Capacitor
C
L1
, C
L2
Frequency Accuracy
Maximum Input Clock Jitter
I²C SERIAL INTERFACE (SDA, SCL)
Serial Clock Frequency
f
SCL
Bus Free Time Between STOP and
t
BUF
START Conditions
5-step staircase
Proper composite
decoder operation
B&W Signal
Color Signal
Fundamental Mode Only
27.0000
4
45
±50
600
0
1.3
External Clock
Page 4 of 83
PARAMETER
SYMBOL
CONDITIONS
MIN
0.6
1.3
0.6
EC Table
TYP
UNITS
MAX
µs
µs
µs
µs
900
300
300
500
400
50
0.4
ns
ns
ns
ns
ns
µs
pF
ns
V
V
Hold Time (repeated) START Condition.
t
HD,STA
SCL Pulse Width Low
t
LOW
SCL Pulse Width High
t
HIGH
Setup Time for a Repeated START
t
SU,STA
0.6
Condition
Data Hold Time
t
HD,DAT
0
Data Setup Time
t
SU,DAT
100
SDA and SCL Receiving Rise Time
t
r
Note 3
20+0.1C
B
SDA and SCL Receiving Fall Time
t
f
Note 3
20+0.1C
B
SDA Transmitting Fall Time
t
f
20+0.1C
B
Setup Time for STOP Condition
t
SU,STO
0.6
Bus Capacitance
C
B
Pulse Width of Suppressed Spike
t
SP
0
HIGH-SPEED LOGIC OUTPUTS (VOUT_<7:0>, PCLK_, TPP_, BCLK_, LRCLK_, SDOUT_, SDIN, SDIO_AL)
Output Low Voltage
V
OL
I
OL
= 2mA, ODS = 01
Output High Voltage
I
OH
= 2mA, ODS = 01
VDDIO –
V
OH
0.4V
Data to Clock Rising Edge Hold Time
VID_<7:0> to PCLK27, ODS = 01
t
HD
VID_<7:0> to PCLK54, ODS = 01
VID_<7:0> to PCLK108, ODS = 01
Data to Clock Rising Edge Setup Time
VID_<7:0> to PCLK27, ODS = 01
t
SU
VID_<7:0> to PCLK54, ODS = 01
VID_<7:0> to PCLK108, ODS = 01
Rise and Fall Time
T
r
, T
f
C
L
=10pF, DVDD_IO=1.8V
(20% to 80%)
C
L
=25pF, DVDD_IO=3.3V
Output Leakage
I
OH,
I
OL
Outputs in High-Z Mode
-3
OPEN-DRAIN LOGIC OUTPUT (SDA)
Output Low Voltage
V
OL
I = 3mA, VDDIO = 1.8V
OL
32.41
13.89
4.63
4.63
4.63
4.63
3
3
±0.01
ns
ns
ns
3
VDDIO
µA
0.2 x
0.4
3
I
OL
= 3mA, VDDIO = 3.3V
Output High Current
I
OH
V
OUT
= 3.3V
±0.01
LOGIC INPUTS (SDA, SCL, DEVADDR <1:0>, BCLK, LRCLK, SDIN, SDIO, FREF, HREF, TCK, TMI, TDS, JTAGRST, REF27I )
Logic Low Threshold
V
IL
Logic High Threshold
Input Leakage Current
SDA/SCL Off Leakage
AUDIO LINE OUT
Audio Output Gain Error
Audio Output Full Scale
Audio Output Dynamic Range
Audio Output THD+N
Audio Output Power Supply Rejection
Ratio
V
IH
I
IH,
I
IL
I
IHI2C
AOGE
AOFS
DR
THDN
PSRA
(T
A
= 25°C)
VDDA=VDDD=VDDIO=0V, SDA=SCL=3.6V
Single ended output
Differential output
0dB gain, single ended output
0dB gain, differential output
Single ended output, Fs = 48kHz
Differential output, Fs = 48kHz
Differential output, Fs = 48kHz
1.7V<V
VDDA
<1.9V, 1.7V<V
VDDD
<1.9V,
1.7V<V
VDDIO
<3.45V, single ended output
1.7V<V
VDDA
<1.9V, 1.7V<V
VDDD
<1.9V,
1.7V<V
VDDIO
<3.45V, differential output
R
L
=10kΩ, no sustained oscillations
DACxHPF = 00
DACxHPF = 01
Page 5 of 83
V
µA
V
V
DVDD_IO
0.3 x
0.7 x
VDDIO
-3
-3
-10
-10
80
80
66
±0.01
±0.01
±1
±1
1
2
90
90
75
74 [80]
74 [80]
100
3
3
10
10
µA
µA
%
Vpp
dB
dB
dB
pF
Audio Output Capacitive Drive
AUDIO DAC HIGHPASS DIGITAL FILTER
Audio Output Cutoff Frequency
f
DHPPB
200
100
Hz
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
