A capacitor to ground sets the LLC soft-start duration
A resistive arrangement sets the maximum and minimum
switching frequencies with opto coupler-based feedback
capabilities.
This pin is low when V
bulk
is ok, opens when V
bulk
passes
below a level adjusted by PGadj pin.
When pulled low, the circuit operates: the PFC starts first and
once FB is in regulation, the LLC is authorized to work. When
left open, the controller is in idle mode.
This pin sets the on and off levels for the PFC powering the
LLC converter
This pin delivers a stable voltage for threshold adjustments
From the Vref pin, a dc level sets the trip point for the PFC
bulk voltage at which the PG out signal is down.
A fully latched OVP monitoring the PFC bulk independently
from FB pin.
Monitors the boost bulk voltage and regulates it. It also serves
as a quick auto-recovery OVP
PFC error amplifier compensation pin
A resistor to ground sets the maximum power level
Line feed forward and PFC brown-out
This pin selects the power level at which the frequency starts
to reduce gradually.
This pin senses the inductor current and also programs the
maximum sense voltage excursion
When pulled above 1 V, the LLC stops and re-starts via a full
soft-start sequence.
This pin is either used as the analog GND for the signal circuit
(A) or for skip operation (B).
The controller ground for the driving loop (A) or the lump
ground pin for all circuits (B)
The driving signal to the PFC power MOSFET
The power supply pin for the controller, 20 V max.
Drive signal for the lower side half-bridge MOSFET
This pin connects to the LLC half-bridge
Drive signal for the upper side half-bridge MOSFET
The bootstrapped V
CC
for the floating driver
3
4
PG out
on/off
The Open-Collector Power
Good Signal
Remote Control
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
BO adj.
Vref
PG adj.
OVP2
FB
V
CTRL
V
M
LBO
Fold
CS
CS/FF
Skip/AGND
GND/PGND
DRV
V
CC
ML
Bridge
MU
V
boot
Brown-Out Adjustment
The 5 V Reference Pin
The Power Good Trip Level
Redundant OVP
PFC Feedback
PFC Error Amplifier Output
PFC Current Amplifier Output
PFC Line Input Voltage Sensing
PFC Fold Back
PFC Current Sense
Fast-Fault Input
Skip (B)/AGND (A)
GND (B)/PGND (A)
PFC Drive Signal
The Controller Supply
Lower-Side MOSFET
Half-Bridge
Upper-Side MOSFET
Bootstrapped Vcc
http://onsemi.com
2
D1
D2
Bulk
Vref
C1
R21
R4
2.2M
C2
R8
U100
R6
R9
1
2
23
22
D5
R16
20
19
18
17
16
15
14
13 R34
8.4k
C15
Over Current
D11
C12
R33
1.2k
R27
39k
C10
0.1u
C11
1n
C13
R28
D12
C14
R29
Vcc
12 V aux.
6
R13
PG adj.
C6
Q1
R12
8
9
10
R19
10
11
R22
12
R25
24k
on/off
U3A
FB
U2A
(*)
R20
10k
0.1u
7
R17
.
T1
M2
.
.
3
BO level
X3
D10
R15
5
R14
Vref
4
C3
L2
24
M1
Power
Good
R5
3.5M
R7
2.2M
R1
3.5M
R3
1.5M
R2
1.5M
L1
D3
D4
D6
X2
PAD2
Vout
C4
R10
R11
D7
D8
C5
V32
V33
D9
U2B
R18
Input
Line
NCP1910
Figure 2. Typical Application Schematic in A Version
http://onsemi.com
(*)
C18
1n
C16
0.1u
C9
1u
C8
R23
0.22u 120k
C17
1n
R24
24k
R32
3.6k
R26
24k
3
C7
U1
R30
R31
0.1
R35
300
*It is recommended to separate the traces of power ground and analog ground. The power ground (pin 17) for driving loop (PFC DRV and LLC ML) is
connected to the PFC MOSFET directly. The analog ground for adjustment components is routed together first and then connected to the analog ground
pin (pin 16) and the PFC sense resistor directly.
D1
L1
Bulk
D2
Vref
C1
R21
R4
2.2M
R7
2.2M
R8
U100
R6
1
2
23
24
R2
1.5M
R1
3.5M
R3
1.5M
C2
Power
Good
R5
3.5M
M1
R9
C3
L2
3
22
D3
D4
D6
X2
PAD2
Vout
C4
M2
D5
4
21
X3
5
20
Vcc
12 V aux.
19
18
17
skip
9
10
15
14
16
BO level
R16
R14
Vref
6
PG adj.
D10
R15
. .
R17
D7
R13
8
7
D8
R10
R11
C5
.
T1
D9
U2B
R18
V32
R12
Q1
C6
0.1u
V33
Input
Line
NCP1910
Figure 3. Typical Application Schematic in B Version
http://onsemi.com
R20
10k
4
(*)
11
R19
10
R22
12
13
C7
R34
8.4k
C15
Over Current
R36
on/off
R25
24k
U3A
D11
C12
R33
1.2k
R27
39k
C11
1n
R28
C13
D12
R29
U1
C14
R30
R31
0.1
FB
(*)
C19
C18
1n
R32
3.6k
C16
0.1u
C9
1u
C8
R23
0.22u 120k
R24
24k
C17
1n
R26
24k
U2A
C10
0.1u
R35
300
*It is recommended to separate the traces of power ground and analog ground. The analog ground traces for adjustment components are routed together first and then
connected to the ground pin (pin 17). The power ground for driving loop (PFC DRV and LLC ML) is connected from ground pin (pin 17) to the PFC sense resistor directly