INTEGRATED CIRCUITS
74F534
Octal D flip-flop, inverting (3-State)
Product specification
Supersedes data of 1999 Jan 08
IC15 Data Handbook
2000 Aug 01
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
FEATURES
•
8-bit positive edge-triggered register
•
3-State inverting output buffers
•
Common 3-State Output register
•
Independent register and 3-State buffer operation
DESCRIPTION
The 74F534 is an 8-bit edge-triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the Clock (CP) and Output Enable (OE) control
gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE
74F534
TYPICAL f
MAX
165MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
51mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL
RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F534N
N74F534D
PKG DWG #
20-Pin Plastic DIP
20-Pin Plastic SOL
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 - D7
OE
CP
Data inputs
Output Enable input (active Low)
Clock Pulse input (active rising edge)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
Q0 - Q7
Data outputs
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
PIN CONFIGURATION
OE 1
Q0
D0
D1
Q1
Q2
D2
D3
Q3
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
LOGIC SYMBOL
3
4
7
8
13
14
17
18
D0
11
CP
D1
D2
D3
D4
D5
D6
D7
1
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND 10
2
V
CC
=Pin 20
GND=Pin 10
5
6
9
12
15
16
19
SF00982
SF00984
2000 Aug 01
2
853-0374 24250
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
LOGIC SYMBOL (IEEE/IEC)
1
11
EN1
C1
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
2D
1
SF00986
LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CP
11
OE
1
2
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
V
CC
=Pin 20
GND=Pin 10
Q0
SF00988
FUNCTION TABLE
INPUTS
OE
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
↑
↑
Dn
l
h
X
X
Dn
INTERNAL
REGISTER
L
H
NC
NC
Dn
OUTPUTS
Q0 – Q7
H
L
NC
Z
Z
OPERATING MODES
Load and read register
Hold
Disable outputs
High voltage level
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
Not a Low-to-High clock transition
2000 Aug 01
3
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
–0.5 to +V
CC
48
0 to +70
–65 to +125
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
LIMITS
MIN
4.5
2.0
0.8
–18
–3
24
70
TYP
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
2000 Aug 01
4
Philips Semiconductors
Product specification
Octal D flip-flop, inverting (3-State)
74F534
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.7V
V
CC
= MAX, V
O
= 0.5V
V
CC
= MAX
–60
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
2.4
2.7
3.3
0.35
0.35
–0.73
0.50
0.50
–1.2
100
20
–0.6
50
–50
–150
TYP
2
MAX
UNIT
V
V
V
V
V
µA
µA
mA
µA
µA
mA
V
O
OH
High-level
High level output voltage
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
Low level output voltage
Low-level
Input clamp voltage
Input current at
maximum input voltage
High-level input current
Low-level input current
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short-circuit output current
3
I
CC
Supply current (total)
V
CC
= MAX
OE=4.5V, Dn=GND
51
86
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
T
amb
= +25°C
V
CC
= +5V
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock frequency
Propagation delay
CP to Qn
Output Enable time
to High or Low level
Output Disable time
from High or Low level
Waveform 1
Waveform 1
Waveform 3
Waveform 4
Waveform 3
Waveform 4
150
3.0
3.0
2.0
2.0
2.0
2.0
TYP
165
4.5
4.5
4.5
5.0
3.5
3.5
7.0
7.0
7.5
7.5
6.5
5.5
MAX
T
amb
= 0°C to +70°C
V
CC
= +5V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
135
2.5
2.5
2.0
2.0
2.0
2.0
7.5
7.5
8.5
8.5
7.5
6.5
MAX
MHz
ns
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
T
amb
= +25°C
V
CC
= +5V
C
L
= 50pF, R
L
= 500Ω
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time,
Dn to CP
Hold time,
Dn to CP
CP pulse width,
High or Low
Waveform 2
Waveform 2
Waveform 1
2.0
2.0
0
0
3.0
3.5
TYP
MAX
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
2.5
2.5
0
0
3.5
4.0
MAX
ns
ns
ns
UNIT
2000 Aug 01
5
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