®
HI5728
Data Sheet
January 22, 2010
FN4321.5
10-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5728 is a 10-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. Operating from a
single +5V or +3V supply, the converter provides 20.48mA of
full scale output current and includes an input data register.
Low glitch energy and excellent frequency domain
performance are achieved using a segmented architecture.
A 60MSPS version and an 8-bit (HI5628) version are also
available. Comparable single DAC solutions are the HI5760
(10-bit) and the HI5660 (8-bit).
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . . . 330mW at 5V, 54mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . .
±1
LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . .
±0.5
LSB
• Gain Matching (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . 0.5%
• SFDR at 5MHz Output . . . . . . . . . . . . . . . . . . . . . . . 68dBc
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
• Internal Voltage Reference
Ordering Information
PART
NUMBER
HI5728IN*
HI5728INZ*
(Note)
HI5728/6IN
HI5728/6INZ
(Note)
HI5728EVAL1
PART
MARKING
HI5728IN
HI5728INZ
HI5728/6IN
TEMP.
RANGE
(°C)
PACKAGE
MAX
CLOCK
SPEED
PKG.
DWG. # (MHz)
125
125
60
60
125
• Dual 10-Bit D/A Converters on a Monolithic Chip
• Pb-Free Available (RoHS Compliant)
Applications
• Wireless Local Loop
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment/Instrumentation
• High Resolution Imaging Systems
-40 to +85 48 Ld LQFP Q48.7x7A
-40 to +85 48 Ld LQFP Q48.7x7A
(Pb-free)
-40 to +85 48 Ld LQFP Q48.7x7A
HI5728 /6INZ -40 to +85 48 Ld LQFP Q48.7x7A
(Pb-free)
+25
Evaluation Platform
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5728
Pin Descriptions
PIN NO.
39, 38, 37, 36,
35, 34, 33, 32,
31, 30
1, 2, 3, 4, 5, 6, 7,
46, 47, 48
8
15
23
22
14, 24
13, 18, 19, 25
17
16
20
21
11, 27
12, 26
10, 28, 41, 44
9, 29, 40, 45
43
42
PIN NAME
PIN DESCRIPTION
QD9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
QD0 (LSB)
channel.
ID9 (MSB) Through
ID0 (LSB)
SLEEP
REFLO
REFIO
FSADJ
ICOMP1, QCOMP1
AGND
IOUTB
IOUTA
QOUTB
QOUTA
NC
AV
DD
DGND
DV
DD
ICLK
QCLK
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pull-down current.
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable.
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x I
FSADJ
.
Reduces noise. Connect each to AV
DD
with 0.1µF capacitor near each pin. The ICOMP1 and QCOMP1
pins MUST be tied together externally.
Analog Ground Connections.
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
Current output of the I channel. Bits set to all 1s gives full scale current.
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
Current output of the Q channel. Bits set to all 1s gives full scale current.
No Connect. Recommended: connect to ground.
Analog Supply (+2.7V to +5.5V).
Digital Ground.
Supply voltage for digital circuitry (+2.7V to +5.5V).
Clock input for I channel. Positive edge of clock latches data.
Clock input for Q channel. Positive edge of clock latches data.
5
FN4321.5
January 22, 2010
嵌入式系统
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