19-2936; Rev 1; 3/06
KIT
ATION
EVALU
BLE
AVAILA
10.7Gbps Adaptive Receive Equalizer
General Description
Features
♦
3mm x 3mm Package
♦
Spans 30in (0.75m) of 6-mil FR-4
♦
Spans 24ft (8m) of Coax
♦
Automatic Receive Equalization to Reduce ISI
Caused by Path Losses
♦
Up to 10.7Gbps NRZ Data Operating Range
♦
Signal-Detect Output
♦
Output-Enable Control
♦
135mW Power Consumption
♦
DC-Coupled Input and Output to Terminations as
Low as 1.65V
♦
Differential or Single-Ended Operation
♦
+3.3V Core Power Supply
MAX3805
The MAX3805 is designed to provide up to 30in
(0.75m) reach on 6-mil differential FR-4 transmission
line, or up to 24ft (8m) on RG-188A/U type coaxial
cable, for PRBS data from 9.95Gbps to 10.7Gbps. The
MAX3805 adaptive equalizer reduces intersymbol inter-
ference, resulting in 20ps residual jitter after equaliza-
tion. An internal feedback network controls the
equalizer to automatically match frequency-dependent
skin effect and dielectric losses. The MAX3805 pro-
vides LVCMOS-compatible output-enable and signal-
detect functions.
The MAX3805 has separate supply connections for the
internal logic and I/O circuits. This allows the current-
mode logic (CML) input and CML output to be connect-
ed to isolated supplies for independent DC-coupled
interfaces to 1.8V, 2.5V, or 3.3V ICs. The MAX3805
comes in a very small 3mm x 3mm package and con-
sumes only 135mW.
Applications
OC-192, 10GbE Switches and Routers
OC-192, 10GbE Serial Modules
High-Speed Signal Distribution
PART
MAX3805ETE
Ordering Information
TEMP RANGE
PIN-
PACKAGE
PACKAGE
CODE
T1633F-3
-40°C to +85°C 16 Thin QFN
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
LINE CARD
2.5V
SWITCH CARD
1.8V
+3.3V
10Gbps
CDR/SERDES
10Gbps
SWITCH
V
CC1
V
CC
V
CC2
Tx
2
+3.3V
FR-4 STRIPLINE
2
PC BOARD
BACKPLANE
SDI
MAX3805
SD EN
SDO
2
2
Rx
V
CC
2
Rx
2
SDO
V
CC2
MAX3805
2
SDI
FR-4 STRIPLINE
2
Tx
SD EN V
CC1
2.5V
1.8V
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10.7Gbps Adaptive Receive Equalizer
MAX3805
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V
CC
) ............................................-0.5V to +4.0V
CML Supply Voltage
(V
CC1
, V
CC2
) ..........................................-0.5V to (V
CC
+ 0.5V)
Current at SDO±...............................................................±25mA
SDI±, EN, SD, HFPD, LFPD........................-0.5V to (V
CC
+ 0.5V)
Current at HFPD, LFPD ......................................................400µA
Continuous Power Dissipation (T
A
= +85°C)
16-Lead QFN-EP (derate 17.5mW/°C
above +85°C) ............................................................1398mW
Operating Ambient Temperature Range .............-40°C to +85°C
Storage Ambient Temperature Range...............-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER
Supply Voltage
Input Termination Voltage
Output Termination Voltage
Operating Ambient Temperature
SYMBOL
V
CC
V
CC1
V
CC2
CONDITIONS
MIN
3.0
1.65
1.65
-40
+25
TYP
3.3
MAX
3.6
V
CC
V
CC
+85
UNITS
V
V
V
°C
ELECTRICAL CHARACTERISTICS
(Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at V
CC
= +3.3V, V
CC1
= V
CC2
= 1.8V, T
A
= +25°C, unless
otherwise noted.) (Values at -40°C are guaranteed by design and characterization.)
PARAMETER
Supply Current
CML Input Differential Voltage
CML Input Common-Mode
Voltage
CML Input Resistance
CML Input Return Loss
CML Output Differential Voltage
CML Output Resistance
CML Output Transition Time
CML Output Return Loss
Equalizer Time Constant
Output Residual Jitter
Signal-Detect Assert
Signal-Detect Deassert
LVCMOS Input-High Leakage
Current
I
H
(Notes 3–6)
PRBS2
31
- 1 at 10.7Gbps (Note 1)
PRBS2
31
SYMBOL
I
CC
V
IN
CONDITIONS
V
CC
= V
CC1
= V
CC2
AC-coupled or DC-coupled at transmission
line input (Notes 1, 6)
MIN
TYP
41
MAX
60
1200
V
CC1
UNITS
mA
mV
P-P
V
Ω
dB
mV
P-P
Ω
ps
dB
µs
400
1.3
Differential
100MHz to 10GHz
V
OUT
t
r
/t
f
V
CC2
= 1.65V to 3.6V
Differential
20% to 80% (Notes 2, 6)
100MHz to 5GHz
85
400
85
100
10
500
100
10
10
21
200
220
115
600
115
35
30
ps
P-P
mV
P-P
mV
P-P
- 1 at 10.7Gbps (Note 1)
+10
+60
µA
2
_______________________________________________________________________________________
10.7Gbps Adaptive Receive Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(Pin 13 (HFPD) and pin 14 (LFPD) are not connected. Typical values are at V
CC
= +3.3V, V
CC1
= V
CC2
= 1.8V, T
A
= +25°C, unless
otherwise noted.) (Values at -40°C are guaranteed by design and characterization.)
PARAMETER
LVCMOS Input-Low Leakage
Current
LVCMOS Input High
LVCMOS Input Low
LVCMOS Output High
LVCMOS Output Low
SYMBOL
I
L
V
IH
V
IL
V
OH
V
OL
I
OH
= 12.5µA
I
OL
= 0.5mA
2.1
0.2
CONDITIONS
MIN
-30
1.5
0.5
TYP
MAX
+30
UNITS
µA
V
V
V
V
MAX3805
Note 1:
Differential input sensitivity is defined at the input to a transmission line with path length up to 30in.
Note 2:
Measured using 10 ones and 10 zeros at 10.7Gbps.
Note 3:
Residual jitter is the difference in total jitter between the signal at the input to the transmission line and the equalizer output.
Total residual jitter is DJ
P-P
+ 14.1
×
RJ
RMS
.
Note 4:
Measured at 10.7Gbps using a pattern of 32 PRBS7, 100 ones, 32 PRBS7 (inverted), 100 zeros.
Note 5:
V
IN
= 400mV
P-P
to 1200mV
P-P
, input path is 0 to 30in, 6-mil microstrip in FR-4,
ε
r
= 4.5, and tan
δ
= 0.02.
Note 6:
Guaranteed by design and characterization.
Typical Operating Characteristics
(V
CC
= 3.3V, V
CC1
= 1.8V, V
CC2
= 1.8V, and T
A
= +25°C, unless otherwise noted.)
EQUALIZER INPUT EYE AFTER 30in OF FR-4
(2
10
- 1PRBS WITH 100 CIDs AT 9.953Gbps)
MAX3805 toc01
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(2
10
- 1PRBS WITH 100 CIDs AT 9.953Gbps)
MAX3805 toc02
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(2
31
- 1PRBS AT 10.7Gbps)
MAX3805 toc03
65mV/div
65mV/div
65mV/div
20ps/div
20ps/div
20ps/div
_______________________________________________________________________________________
3
10.7Gbps Adaptive Receive Equalizer
MAX3805
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, V
CC1
= 1.8V, V
CC2
= 1.8V, and T
A
= +25°C, unless otherwise noted.)
EQUALIZER OUTPUT EYE AFTER 30in OF FR-4
(CJTPAT 10.0Gbps LFPD/(HFPD + LFPD) = 0.6)
MAX3805 toc04
EQUALIZER OUTPUT EYE AFTER
24ft OF RG-188/U COAXIAL CABLE,
SINGLE ENDED (2
23
- 1PRBS AT 10.7Gbps)
MAX3805 toc05
SUPPLY CURRENT vs. TEMPERATURE
V
CC
= V
CC1
= V
CC2
= +3.3V
60
SUPPLY CURRENT (mA)
55
50
45
40
35
MAX3805 toc06
65
65mV/div
65mV/div
20ps/div
20ps/div
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
RESIDUAL JITTER vs. AMPLITUDE
MAX3805 toc07
RESIDUAL JITTER
vs. FR-4 PATH LENGTH
DATA RATE = 10.7Gbps
PATTERN = PRBS 2
10
-1
V
IN
= 400mV
P-P
MAX3805 toc08
50
45
RESIDUAL JITTER (ps)
40
35
DATA RATE = 9.953Gbps
PATTERN = PRBS 2
10
-1
50
45
RESIDUAL JITTER
40
35
30
25
20
RESIDUAL JITTER = DJ + 14.1 x RJ
30
25
20
FR4 = 18in
15
400 500 600 700 800
900 1000 1100 1200
AMPLITUDE (mV
P-P
)
FR4 = 30in
RESIDUAL JITTER = DJ + 14.1 x RJ
15
3
6
9
12
15
18
21
24
27
30
FR-4 PATH LENGTH (in)
RESIDUAL JITTER vs. DATA RATE
MAX3805 toc09
RESIDUAL JITTER
vs. R
LFPD
/(R
HFPD
+ R
LFPD
)
V
IN
= 400mV
P-P
PATTERN = CJTPAT
DATA RATE = 10.0Gbps
(R
LFPD
+ R
HFPD
) = 100kΩ
MAX3805 toc10
50
45
RESIDUAL JITTER (ps)
40
35
30
25
20
15
50
45
RESIDUAL JITTER (ps)
40
35
30
25
20
V
IN
= 400mV
P-P
PATTERN = 100 1's PRBS 2
10
-1
100 0's PRBS 2
10
-1
RESIDUAL JITTER = DJ + 14.1
x
RJ
18in FR4
30in FR4
18in FR4
10
6
7
8
9
10
11
DATA RATE (Gbps)
15
RESIDUAL JITTER = DJ + 14.1 x RJ
0.5
0.6
0.7
30in FR4
0.8
0.9
R
LFPD
/(R
HFPD
+ R
LFPD
)
4
_______________________________________________________________________________________
10.7Gbps Adaptive Receive Equalizer
Pin Description
PIN
1
2
3
4
5
6
7
8
9, 12
10
11
13
14
15
16
EP
NAME
V
CC1
SDI+
SDI-
V
CC1
GND
SD
EN
GND
V
CC2
SDO-
SDO+
HFPD
LFPD
V
CC
GND
Exposed
Pad
Supply Voltage, CML Input (1.8V to V
CC
)
Positive Differential Serial Data Input, CML
Negative Differential Serial Data Input, CML
Supply Voltage, CML Input (1.8V to V
CC
)
Supply Ground
Signal-Detect Output, LVCMOS. Low indicates <200mV
P-P
, high indicates >220mV
P-P
.
Enable Input, LVCMOS. Low disables output, high enables output, typically connected to SD.
Supply Ground
Supply Voltage, CML Output (1.8V to V
CC
)
Negative Differential Serial Data Output, CML
Positive Differential Serial Data Output, CML
High-Frequency Power Detector. Leave open for 9.95Gbps to 10.7Gbps PRBS NRZ data.
Low-Frequency Power Detector. Leave open for 9.95Gbps to 10.7Gbps PRBS NRZ data.
Supply Voltage, Equalizer Core, 3.3V
Supply Ground
Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and
electrical performance.
FUNCTION
MAX3805
Detailed Description and
Applications Information
The MAX3805 adaptive equalizer is designed to oper-
ate with 9.95Gbps to 10.7Gbps PRBS nonreturn-to-zero
(NRZ) data at the receive end of a transmission line,
typically differential 6-mil FR-4 PC board. It adaptively
corrects intersymbol interference caused by frequency-
dependent path loss. It can also be used with coaxial
cable links and with transmission lines that include well-
engineered connectors, as long as the total path loss is
relatively smooth and does not exceed 20dB at 5GHz.
The signal path for the MAX3805 consists of a CML
input stage, two amplifiers feeding a pair of variable
attenuators controlled by feedback, and a limiting
amplifier with a CML output stage. An enable input, EN,
is used to control the output stage. A signal-detect out-
put, SD, indicates when input signal to the transmission
line is above 220mV
P-P
or below 200mV
P-P
, typically.
See the
Functional Diagram.
CML Input and Output Buffers
The MAX3805 CML input and output buffers are inter-
nally terminated with 50Ω to V
CC1
and V
CC2
, respec-
tively. The input and output circuitry have separate
voltage connections to control noise coupling and pro-
vide DC-coupling to +1.8V, +2.5V, or +3.3V CML. If
desired, the CML inputs and outputs can be AC-cou-
pled. See Figure 1 for the output structure.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
For single-ended operation (typically coaxial cable
links), the input must be AC-coupled; connect the
unused input to V
CC1
using a series combination of an
AC-coupling capacitor and a 50Ω resistor, as shown in
Figure 2. Note that the MAX3805 is specified for differ-
ential operation, and the performance may be reduced
in single-ended operation.
_______________________________________________________________________________________
5
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