CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM
CY7C144AV
CY7C006AV
3.3 V 8 K / 16 K × 8
Asynchronous Dual-Port Static RAM
3.3 V 8 K / 16 K × 8 Dual-Port Static RAM
Features
■
■
■
■
■
■
■
■
■
■
■
■
Expandable data bus to 16 bits or more using Master/ Slave
chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Pin select for Master or Slave
Available in 64-pin thin quad flat pack (TQFP) (7C006AV and
7C144AV)
Pb-free packages available
True dual-ported memory cells which allow simultaneous
access of the same memory location
8 K / 16 K × 8 organizations (CY7C144AV/CY7C006AV)
0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed access: 25 ns
Low operating power
❐
Active: I
CC
= 115 mA (typical)
❐
Standby: I
SB3
= 10
A
(typical)
Fully asynchronous operation
Automatic power-down
■
■
Functional Description
For a complete list of related documentation,
click here.
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
I/O
0L
–I/O
7L
[1]
8
8
I/O
Control
I/O
Control
I/O
0R
–I/O
7R
[1]
A
0L
–A
12–13L
[2]
13–14
Address
Decode
13–14
True Dual-Ported
RAM Array
Address
Decode
13–14
13–14
A
0R
–A
12–13R
[2]
[2]
A
0L
–A
12–13L
CE
L
OE
L
R/W
L
SEM
L
Interrupt
Semaphore
Arbitration
[3]
A
0R
–A
12–13R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
[2]
BUSY
L
INT
L
[3]
M/S
Notes
1. I/O
0
–I/O
7
for × 8 devices.
2. A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
3. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document Number: 38-06051 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 14, 2015
CY7C144AV
CY7C006AV
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 4
Pin Definitions .................................................................. 4
Architecture ...................................................................... 4
Functional Overview ........................................................ 4
Read and Write Operations ......................................... 4
Interrupts ..................................................................... 5
Busy ............................................................................ 5
Master/Slave ............................................................... 5
Semaphore Operation ................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
Electrical Characteristics ................................................. 6
Capacitance ...................................................................... 6
AC Test Loads and Waveforms ....................................... 7
Data Retention Mode ........................................................ 7
Timing ................................................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms .................................................... 10
Non-Contending Read/Write .......................................... 16
Interrupt Operation Example ......................................... 16
Semaphore Operation Example .................................... 16
Ordering Information ...................................................... 17
8 K × 8 3.3 V Asynchronous Dual-Port SRAM .......... 17
16 K × 8 3.3 V Asynchronous Dual-Port SRAM ........ 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Document Number: 38-06051 Rev. *J
Page 2 of 21
CY7C144AV
CY7C006AV
Pin Configurations
Figure 1. 64-pin TQFP pinout (Top View)
SEM
L
R/W
L
I/O
1L
I/O
0L
A
12L
A
11L
A
10L
OE
L
CE
L
NC
V
CC
A
9L
A
8L
52
A
7L
A
6L
A
5L
49
64
63
62
61
60
59
58
57
56
55
54
53
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
51
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
CY7C144AV (8 K × 8)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
7R
A
8L
A
7L
52
R/W
R
SEM
R
CE
R
NC
I/O
6R
GND
A
9R
A
8R
OE
R
A
12R
Figure 2. 64-pin TQFP pinout (Top View)
SEM
L
R/W
L
I/O
1L
I/O
0L
I/O
7R
CE
L
A
13L
A
12L
A
11L
A
10L
OE
L
V
CC
A
11R
A
10R
A
9L
64
63
62
61
60
59
58
57
56
55
54
53
51
50
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
49
A
6L
A
5L
A
6R
A
5R
32
16
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
CY7C006AV (16 K × 8)
41
40
39
38
37
36
35
34
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
7R
R/W
R
SEM
R
I/O
6R
CE
R
A
13R
A
9R
A
8R
GND
A
12R
Document Number: 38-06051 Rev. *J
I/O
7R
A
11R
A
10R
OE
R
A
6R
A
5R
32
16
33
Page 3 of 21
CY7C144AV
CY7C006AV
Selection Guide
Description
Maximum access time (ns)
Typical operating current (mA)
Typical standby current for I
SB1
(mA) (Both ports TTL level)
Typical standby current for I
SB3
(A) (Both ports CMOS level)
CY7C144AV/CY7C006AV
-25
25
115
30
10
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
12/13L
I/O
0L
–I/O
7L
SEM
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
Right Port
CE
R
R/W
R
OE
R
A
0R
–A
12/13R
I/O
0R
–I/O
7R
SEM
R
INT
R
BUSY
R
Chip enable
Read/Write enable
Output enable
Address (A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices)
Data bus input/output (I/O
0
–I/O
7
for × 8 devices)
Semaphore Enable
Interrupt flag
Busy flag
Master or Slave select
Power
Ground
No connect
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
logic.
Application
areas
include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a Chip Select (CE) pin.
Description
Architecture
The CY7C144AV and CY7C006AV consist of an array of 8K and
16K words of 8 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two interrupt
(INT) pins can be utilized for port-to-port communication. Two
semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the device can function as a master
(BUSY pins are outputs) or as a slave (BUSY pins are inputs).
The device also has an automatic power-down feature controlled
by CE. Each port is provided with its own output enable control
(OE), which allows data to be read from the device.
Functional Overview
The CY7C144AV and CY7C006AV are low-power CMOS
8 K / 16 K × 8 dual-port static RAMs. Various arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 8-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16-bit or wider
Document Number: 38-06051 Rev. *J
Read and Write Operations
When writing data must be set up for a duration of t
SD
before the
rising edge of R/W in order to guarantee a valid write. A write
operation is controlled by either the R/W pin (see Write Cycle No.
1 waveform) or the CE pin (see Write Cycle No. 2 waveform).
Page 4 of 21
CY7C144AV
CY7C006AV
Required inputs for non-contention operations are summarized
in
Table 1 on page 16.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port t
DDD
after the data is presented on the other port.
When reading the device, the user must assert both the OE and
CE pins. Data will be available t
ACE
after CE or t
DOE
after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin and OE must
also be asserted.
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C144AV and CY7C006AV provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t
SOP
before attempting to read the semaphore.
The semaphore value will be available t
SWRD
+ t
DOE
after the
rising edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel
its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
0–2
represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
0
is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it.
Table 3 on page 16
shows sample
semaphore operations.
When reading a semaphore, all data lines output the semaphore
value. The read value is latched in an output register to prevent
the semaphore from changing state during a write from the other
port. If both ports attempt to access the semaphore within t
SPS
of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (1FFF for the
CY7C144AV and 3FFF for the CY7C006AV) is the mailbox for
the right port and the second-highest memory location (1FFE for
the CY7C144AV and 3FFE for the CY7C006AV) is the mailbox
for the left port. When one port writes to the other port’s mailbox,
an interrupt is generated to the owner. The interrupt is reset when
the owner reads the contents of the mailbox. The message is
user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it. If an application
does not require message passing, do not connect the interrupt
pin to the processor’s interrupt request input pin. The operation
of the interrupts and their interaction with Busy are summarized
in
Table 2 on page 16.
Busy
The CY7C144AV and CY7C006AV provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ CEs are asserted and an address match occurs within
t
PS
of each other, the busy logic will determine which port has
access. If t
PS
is violated, one port will definitely gain permission
to the location, but it is not predictable which port will get that
permission. BUSY will be asserted t
BLA
after an address match
or t
BLC
after CE is taken LOW.
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (t
BLC
or t
BLA
), otherwise,
Document Number: 38-06051 Rev. *J
Page 5 of 21
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