电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

SI5418DU-T1-GE3

产品描述Darlington Transistors TRANSISTOR ARRAYS
产品类别分立半导体    晶体管   
文件大小143KB,共9页
制造商Vishay(威世)
官网地址http://www.vishay.com
标准
下载文档 详细参数 全文预览

SI5418DU-T1-GE3在线购买

供应商 器件名称 价格 最低购买 库存  
SI5418DU-T1-GE3 - - 点击查看 点击购买

SI5418DU-T1-GE3概述

Darlington Transistors TRANSISTOR ARRAYS

SI5418DU-T1-GE3规格参数

参数名称属性值
是否Rohs认证符合
包装说明SMALL OUTLINE, R-PDSO-N3
针数8
Reach Compliance Codecompliant
ECCN代码EAR99
外壳连接DRAIN
配置SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压30 V
最大漏极电流 (ID)11.6 A
最大漏源导通电阻0.0145 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JESD-30 代码R-PDSO-N3
JESD-609代码e3
湿度敏感等级1
元件数量1
端子数量3
工作模式ENHANCEMENT MODE
最高工作温度150 °C
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)260
极性/信道类型N-CHANNEL
最大脉冲漏极电流 (IDM)40 A
认证状态Not Qualified
表面贴装YES
端子面层MATTE TIN
端子形式NO LEAD
端子位置DUAL
处于峰值回流温度下的最长时间40
晶体管应用SWITCHING
晶体管元件材料SILICON
Base Number Matches1

文档预览

下载PDF文档
New Product
Si5418DU
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
PRODUCT SUMMARY
V
DS
(V)
30
R
DS(on)
(Ω)
0.0145 at V
GS
= 10 V
0.0185 at V
GS
= 4.5 V
I
D
(A)
a
12
12
Q
g
(Typ.)
9.5 nC
FEATURES
Halogen-free
TrenchFET
®
Power MOSFET
• New Thermally Enhanced PowerPAK
®
ChipFET
®
Package
- Small Footprint Area
- Low On-Resistance
- Thin 0.8 mm Profile
RoHS
COMPLIANT
PowerPAK ChipFET Single
1
2
D
D
D
D
D
D
G
S
S
Marking Code
3
4
AI
XXX
Lot Traceability
and Date Code
Part # Code
APPLICATIONS
• Load Switch, PA Switch, and Battery
Switch for Portable Applications
• DC-DC Synchronous Rectification
G
D
8
7
6
5
Bottom View
Ordering Information:
Si5418DU-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
T
C
= 25 °C
Continuous Drain Current (T
J
= 150 °C)
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
T
C
= 25 °C
T
A
= 25 °C
T
C
= 25 °C
Maximum Power Dissipation
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
d, e
T
J
, T
stg
P
D
I
DM
I
S
I
D
Symbol
V
DS
V
GS
Limit
30
± 20
12
a
12
a
11.6
b, c
9.3
b, c
40
12
a
2.6
b, c
31
20
3.1
b, c
2
b, c
- 55 to 150
260
W
A
Unit
V
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
b, f
Maximum Junction-to-Case (Drain)
t
5s
Steady State
Symbol
R
thJA
R
thJC
Typical
34
3
Maximum
40
4
Unit
°C/W
Notes:
a. Package limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See Solder Profile (
http://www.vishay.com/ppg?73257
). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 90 °C/W.
Document Number: 69822
S-81448-Rev. B, 23-Jun-08
www.vishay.com
1

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1782  1014  2833  16  148  28  1  59  40  14 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved