74AVCH16245
16-bit transceiver with direction pin; 3.6 V tolerant; 3-state
Rev. 3 — 8 January 2013
Product data sheet
1. General description
The 74AVCH16245 is a 16-bit transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions. The device features two output enable inputs
(nOE) for easy cascading and two send/receive inputs (nDIR) for direction control.
Inputs nOE control the outputs so that the buses are effectively isolated. This device can
be used as two 8-bit transceivers or one 16-bit transceiver.
The 74AVCH16245 is designed to have an extremely fast propagation delay and a
minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, tie pins nOE
to V
CC
through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line
drive during transient (see
Figure 4
and
Figure 5)
The 74AVCH16245 has active bus-hold circuitry to hold unused or floating data inputs at a
valid logic level. This feature eliminates the need for external pull-up or pull-down
resistors.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-1A (2.7 V to 3.6 V)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,
resulting in noise reduction without speed degradation
Low inductance multiple VCC and GND pins to minimize noise and ground bounce
Supports Live Insertion
All inputs have bus-hold
NXP Semiconductors
74AVCH16245
16-bit transceiver with direction pin; 3.6 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AVCH16245DGG
40 C
to +85
C
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
Type number
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa789
Fig 1.
Logic symbol
74AVCH16245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 January 2013
2 of 16
NXP Semiconductors
74AVCH16245
16-bit transceiver with direction pin; 3.6 V tolerant; 3-state
1OE
1DIR
2OE
2DIR
G3
3EN1[BA]
3EN2[AB]
G6
6EN1[BA]
6EN2[AB]
1A0
1
2
1B0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aaa790
Fig 2.
IEC logic symbol
74AVCH16245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 January 2013
3 of 16
NXP Semiconductors
74AVCH16245
16-bit transceiver with direction pin; 3.6 V tolerant; 3-state
5. Pinning information
5.1 Pinning
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*1'
%
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9
&&
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2(
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$
*1'
$
$
9
&&
$
$
*1'
$
$
$
$
*1'
$
$
9
&&
$
$
*1'
$
$
2(
DDD
*1'
%
%
%
%
*1'
%
%
9
&&
%
%
*1'
%
%
',5
Fig 3.
Pin configuration
74AVCH16245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 January 2013
4 of 16
NXP Semiconductors
74AVCH16245
16-bit transceiver with direction pin; 3.6 V tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
1DIR, 2DIR
1B0 to 1B7
2B0 to 2B7
GND
V
CC
1OE, 2OE
1A0 to 1A7
2A0 to 2A7
Pin description
Pin
1, 24
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
48, 25
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
Description
direction control input
data input/output
data input/output
ground (0 V)
supply voltage
output enable input (active LOW)
data input/output
data input/output
6. Functional description
Table 3.
Inputs
nOE
L
L
H
[1]
Function table
[1]
Outputs
nDIR
L
H
X
nAn
A=B
inputs
Z
nBn
inputs
B=A
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
[1]
Max
+4.6
-
+4.6
-
V
CC
+ 0.5
+4.6
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
< 0 V
output HIGH or LOW
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
74AVCH16245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 January 2013
5 of 16
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