CY7C1481BV33
72-Mbit (2M × 36) Flow-Through SRAM
72-Mbit (2M × 36) Flow-Through SRAM
Features
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Functional Description
The CY7C1481BV33 is a 3.3 V, 2M × 36 synchronous flow
through SRAM designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive edge triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
Chip Enable (CE
1
), depth expansion Chip Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW
x
and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1481BV33 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1481BV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC standard JESD8-5 compatible.
For a complete list of related documentation, click
here.
Supports 133 MHz bus operations
2M × 36 common I/O
3.3 V core power supply (V
DD
)
2.5 V or 3.3 V I/O supply (V
DDQ
)
Fast clock to output time
❐
6.5 ns (133 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
CY7C1481BV33 available in JEDEC standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
IEEE 1149.1 JTAG compatible boundary scan
ZZ sleep mode option
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
335
150
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-74857 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 2, 2018
CY7C1481BV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
Boundary Scan Exit Order ............................................. 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Timing Diagrams ............................................................ 22
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Document Number: 001-74857 Rev. *F
Page 3 of 31
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