EVALUATION KIT AVAILABLE
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
General Description
The MAX5318 is a high-accuracy, 18-bit, serial SPI input,
buffered voltage output digital-to-analog converter (DAC)
in a 4.4mm x 7.8mm, 24-lead TSSOP package. The
device features
Q2
LSB INL (max) accuracy and a
Q1
LSB DNL (max) accuracy over the full temperature range
of -40NC to +105NC.
The DAC voltage output is buffered resulting in a fast
settling time of 3Fs and a low offset and gain drift of
Q0.5ppm/NC
of FSR (typ). The force-sense output (OUT)
maintains accuracy while driving loads with long lead
lengths. Additionally, a separate AVSS supply, allows the
output amplifier to go to 0V (GND) while maintaining full
linearity performance.
The MAX5318 includes user-programmable digital gain
and offset correction to enable easy system calibration.
At power-up, the device resets its outputs to zero or mid-
scale. The wide 2.7V to 5.5V supply voltage range and
integrated low-drift, low-noise reference buffer amplifier
make for ease of use.
The MAX5318 features a 50MHz 3-wire SPI interface. The
MAX5318 is available in a 24-lead TSSOP package and
operates over the -40NC to +105NC temperature range.
Benefits and Features
S
Ideal for ATE and High-Precision Instruments
Accuracy Guaranteed with
±2
LSB (Max)
INL
Over Temperature
S
Fast Settling Time (3µs) with 10kI || 100pF Load
S
Safe Power-Up-Reset to Zero or Midscale DAC
Output (Pin-Selectable)
Predetermined Output Device State in Power-Up
and Reset in System Design
S
Negative Supply (AVSS) Option Allows Full INL
and DNL Performance to 0V
S
SPI Interface Compatible with 1.8V to 5.5V Logic
S
High Integration Reduces Development Time and
PCB Area
Buffered Voltage Output Directly Drives
2kI Load Rail-to-Rail
Integrated Reference Buffer
No External Amplifiers Required
S
Small 4.4mm x 7.8mm, 24-Pin TSSOP Package
Ordering Information
and
Typical Operating Circuit
appear
at end of data sheet.
Applications
Test and Measurement
Equipment
Automatic Test Equipment
Gain and Offset
Adjustment
Data-Acquisition Systems
Process Control and
Servo Loops
SPI
Programmable Voltage
and Current Sources
Automatic Tuning and
Calibration
Communication Systems
Medical Imaging
LDAC
5
Functional Diagram
V
DDIO
24
REF
18
AVDD1
14
AVDD2
21
17
REFO
MAX5318
BUFFER
CS 9
SCLK 8
DIN 7
DOUT 6
READY 2
DIGITAL
OFFSET
SPI
INTERFACE
DIGITAL
GAIN
DIN
INPUT/DAC
REGISTER
18-BIT
DAC
7.8kI
7.8kI
7.8kI
16
RFB
For related parts and recommended products to use with this part,
refer to
www.maximintegrated.com/MAX5318.related.
BUSY
RST
M/Z
TC/SB
PD
4
1
3
10
11
23
OUTPUT
BUFFER
15
OUT
CONTROL
LOGIC
POWER-ON
RESET
SHUTDOWN
22
13
19
7.8kI
20
12
DGND
BYPASS
AGND
AGND_S
AGND_F
AVSS
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6465; Rev 0; 9/12
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ABSOLUTE MAXIMUM RATINGS
AGND to DGND ...................................................-0.3V to +0.3V
AGND_F, AGND_S to AGND ...............................-0.3V to +0.3V
AGND_F, AGND_S to DGND ...............................-0.3V to +0.3V
AVDD to AGND .......................................................-0.3V to +6V
AVDD to REF ...........................................................-0.3V to +6V
AVSS to AGND ........................................................-2V to +0.3V
V
DDIO
to DGND.......................................................-0.3V to +6V
BYPASS to DGND ....................................... -0.3V to the lower of
(V
AVDD_
or V
DDIO
+ 0.3V) and +4.5V
OUT, REFO, RFB to AGND ......................... -0.3V to the lower of
(V
AVDD
+ 0.3V) and +6V
REF to AGND ...................-0.3V to the lower of V
AVDD
and +6V
SCLK, DIN,
CS, BUSY, LDAC, READY,
M/Z, TC/SB,
RST,
PD, DOUT to DGND....... -0.3V to the lower of
(V
DDIO
+ 0.3V) and +6V
Continuous Power Dissipation (T
A
= +70NC)
TSSOP (derate 13.9mW/NC above +70NC).............1111.1mW
Operating Temperature Range ........................ -40NC to +105NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Case Thermal Resistance (q
JA
) ...............13°C/W
Junction-to-Ambient Thermal Resistance (q
JA
) ..........72°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
DDIO
=
4.5V to 5.5V,
V
AVSS
= -1.25V, V
AGND
= V
DGND
= V
AGND_F
= V
AGND_S
= 0V, V
REF
= 4.096V, TC/SB =
PD =
LDAC
= M/Z = DGND,
RST
= V
DDIO
, C
REFO
= 100pF, C
L
= 100pF, R
L
= 10kω, C
BYPASS
= 1µF, T
A
= -40°C to +105°C, unless
otherwise noted. Typical values are at T
A
= +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER
STATIC PERFORMANCE
Resolution
N
DIN = 0x00000 to 0x3FFFF
(binary mode), DIN = 0x20000 to 0x1FFFF
(two’s complement mode)
DIN = 0x01900 to 0x3FFFF (binary
mode), DIN = 0x21900 to 0x1FFFF (two’s
complement mode), V
AVSS
= 0V
DIN = 0, T
A
= +25NC
DIN = 0, T
A
= -40NC to +105NC
DIN = 0
T
A
= +25NC
T
A
= -40NC to +105NC
-2.5
No load
0
18
Bits
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Integral Nonlinearity (Note 3)
INL
-2
Q0.5
+2
LSB
Differential Nonlinearity (Note 3)
Zero Code Error
Zero Code Error Drift (Note 4)
Gain Error
Gain Error Temperature
Coefficient (Note 4)
Output Voltage Range
DNL
OE
-1
-48
-1.6
-16
Q0.275
Q4
Q14
Q0.10
Q1
Q27
Q0.10
+1
+48
+1.6
+16
LSB
LSB
ppm/NC
LSB
ppm/NC
of FSR
V
GE
TCGE
+2.5
V
AVDD
-
0.1
Maxim Integrated
2
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DDIO
=
4.5V to 5.5V,
V
AVSS
= -1.25V, V
AGND
= V
DGND
= V
AGND_F
= V
AGND_S
= 0V, V
REF
= 4.096V, TC/SB =
PD =
LDAC
= M/Z = DGND,
RST
= V
DDIO
, C
REFO
= 100pF, C
L
= 100pF, R
L
= 10kω, C
BYPASS
= 1µF, T
A
= -40°C to +105°C, unless
otherwise noted. Typical values are at T
A
= +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER
SYMBOL
CONDITIONS
RST
= pulse low
RST
= pulse low,
V
AVSS
= 0V
RST
= DGND
RST
= DGND,
V
AVSS
= 0V
DC Output Impedance (Normal
Mode)
Output Resistance (Power-Down
Mode)
Output Current
I
OUT
C
L
R
L
I
SC
T
SC
DC PSRR
For specified performance
OUT shorted to AGND or AVDD
Short-Circuit Current
Short-Circuit Duration
DC Power-Supply Rejection
REFO shorted to AGND or AVDD
BYPASS shorted to AGND or AVDD
Short to AGND or AVDD
V
OUT
at full scale, V
AVDD
= 4.5V to 5.5V
V
AVSS
= -1.5V to -0.5V
-2.5
-2.5
2
Q60
Q65
Q48
Indefinite
MIN
TYP
75
2.048
10
2.048
-68
2.036
10
2.036
4
2
Q4
MAX
UNITS
FV
V
mV
V
mV
V
mV
V
mI
kI
M/Z = DGND
M/Z = V
DDIO
M/Z = DGND
M/Z = V
DDIO
M/Z = DGND
M/Z = V
DDIO
M/Z = DGND
Reset Voltage Output
V
OUT-RESET
R
OUT
M/Z = V
DDIO
Closed-loop connection (RFB connected
to OUT)
PD = V
DDIO
Source/sink within 100mV of the supply
rails
Source/sink within 800mV of the supply
rails
mA
Q25
200
pF
kI
mA
s
+2.5
+2.5
V
AVDD
-
0.1
10
10
Q0.15
V
AVDD
-
0.1
500
LSB/V
Load Capacitance to GND
Load Resistance to GND
Q0.20
Q0.012
STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION
Reference High Input Range
Reference Input Capacitance
Reference Input Resistance
Reference Input Current
V
REF
C
REF
R
REF
I
B
2.4
2.4
V
pF
MI
FA
STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION
Reference High Output Range
Reference High Output Load
Regulation
Reference Output Capacitor
R
ESR
< 5I
V
ppm/
mA
nF
0.1
Maxim Integrated
3
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DDIO
=
4.5V to 5.5V,
V
AVSS
= -1.25V, V
AGND
= V
DGND
= V
AGND_F
= V
AGND_S
= 0V, V
REF
= 4.096V, TC/SB =
PD =
LDAC
= M/Z = DGND,
RST
= V
DDIO
, C
REFO
= 100pF, C
L
= 100pF, R
L
= 10kω, C
BYPASS
= 1µF, T
A
= -40°C to +105°C, unless
otherwise noted. Typical values are at T
A
= +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER
Output Voltage
Load Capacitance to GND
POWER-SUPPLY REQUIREMENTS
Positive Analog Power-Supply
Range
Digital Interface Power-Supply
Range
Negative Analog Power-Supply
Range
Positive Analog Power-Supply
Current
Negative Analog Power-Supply
Current
Interface Power-Supply Current
Positive Analog Power-Supply
Power-Down Current
Negative Analog Power-Supply
Power-Down Current
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
From 10% to 90% full scale, positive and
negative transitions
From falling edge of LDAC to within
0.003% FS, R
L
= 10kI, DIN = 04000h
(6.25% FS) to 3C000h (93.75% FS)
(Note 5)
Major code transition (1FFFFh to 20000h),
R
L
= 10kI, C
L
= 50pF
CSB = V
DDIO
, f
SCLK
= 1kHz, all digital
inputs from 0V to V
DDIO
At f = 1kHz to 10kHz, without reference,
code = 20000h
At f = 0.1Hz to 10Hz, without reference,
code = 20000h
From power-down mode
From power-off
4.9
V/Fs
V
AVDD
V
DDIO
V
AVSS
I
AVDD
I
AVSS
I
VDDIO
No load, external reference, output at zero
scale
No load, external reference, output at zero
scale
Digital inputs at V
DDIO
or DGND
PD = V
DDIO
, power-down mode
PD = V
DDIO
, power-down mode
-5
-1.5
4.5
1.8
-1.5
-1.25
5.2
-1.0
0.2
20
-3
5.0
50
5.5
V
AVDD
0
6.5
V
V
V
mA
mA
FA
FA
FA
SYMBOL
V
BYPASS
C
L
Required for stability, R
ESR
= 0.1I (typ)
CONDITIONS
MIN
2.3
1
TYP
2.4
MAX
2.5
8
UNITS
V
FF
STATIC PERFORMANCE—V
BYPASS
OUT SECTION
Voltage Output Settling Time
Busy Time
DAC Glitch Impulse
Digital Feed Through
Output Voltage-Noise Spectral
Density
Output Voltage Noise
Wake-Up Time
Power-Up Time
t
S
t
BUSY
3
1.9
4
1
26
1.55
75
2
Fs
Fs
nVs
nVs
nV/√Hz
FV
P-P
Fs
ms
Maxim Integrated
4
MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
DDIO
=
2.7V to 3.3V,
V
AVSS
= -1.25V, V
AGND
= V
DGND
= V
AGND_F
= V
AGND_S
= 0V, V
REF
= 2.5V, TC/SB = PD =
LDAC
=
M/Z = DGND,
RST
= V
DDIO
, C
REFO
= 100pF, C
L
= 100pF, R
L
= 10kω, C
BYPASS
= 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000,
T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2)
PARAMETER
STATIC PERFORMANCE
Resolution
N
DIN = 0x00000 to 0x3FFFF (binary
mode), DIN = 0x20000 to 0x1FFFF (two’s
complement mode)
DIN = 0x01900 to 0x3FFFF (binary
mode), DIN = 0x21900 to 0x1FFFF (two’s
complement mode), V
AVSS
= 0V
DIN = 0, T
A
= +25NC
DIN = 0, T
A
= -40NC to +105NC
DIN = 0
GE
TCGE
No load
RST
= pulse low
RST
= pulse low,
V
AVSS
= 0V
RST
= DGND
RST
= DGND,
V
AVSS
= 0V
DC Output Impedance
Output Current
Load Capacitance to GND
Load Resistance to GND
Short-Circuit Current
Short-Circuit Duration
R
OUT
I
OUT
C
L
R
L
I
SC
t
SC
For specified performance
OUT shorted to AGND or AVDD
REFO shorted to AGND or AVDD
BYPASS shorted to AGND or AVDD
Short to AGND or AVDD
2
Q60
Q65
Q48
Indefinite
SYMBOL
CONDITIONS
MIN
18
TYP
MAX
UNITS
Bits
Integral Nonlinearity (Note 3)
INL
-2.0
Q0.75
+2.0
LSB
Differential Nonlinearity (Note 3)
Zero Code Error
Zero Code Error Drift (Note 4)
Gain Error
Gain Error Temperature
Coefficient (Note 4)
Output Voltage Range
DNL
OE
-1.0
-50
-2.7
-16
Q0.3
Q6
Q25
Q1.4
Q1.5
Q35
+1.0
+50
+2.7
+16
LSB
LSB
ppm/NC
LSB
ppm/NC
of FSR
V
FV
V
mV
V
mV
V
mV
V
mI
mA
T
A
= +25NC
T
A
= -40NC to +105NC
-3.2
0
M/Z = DGND
M/Z = V
DDIO
M/Z = DGND
M/Z = V
DDIO
M/Z = DGND
M/Z = V
DDIO
M/Z = DGND
M/Z = V
DDIO
75
1.25
10
1.25
-40
1.25
10
1.24
4
Q4
Q25
+3.2
V
AVDD
-
0.1
Reset Voltage Output
V
OUT-RESET
Closed-loop connection, RFB connected
to OUT
Source/sink within 100mV of the supply rails
Source/sink within 800mV of the supply rails
200
pF
kI
mA
s
Maxim Integrated
5
FPGA/CPLD
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