Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= 0°C to +85°C,
unless otherwise noted.)
PARAMETER
GENERAL
Input Supply Range
V
IN
Undervoltage Lockout
Operating Supply Current
V
IN
Shutdown Supply Current
Input Resistance for CS+/CS-
Current-Limit Threshold
for CS+/CS-
Common-Mode Rejection
of Current Threshold
Gate-Driver Resistance
FB Input Bias Current
FB Voltage
FB Voltage
Temperature Coefficient
FB to COMP Transconductance
COMP Pulldown Resistance
in Shutdown
DACOUT to FB Voltage Difference
DACOUT Differential Nonlinearity
(Note 1)
DACOUT Voltage Temperature
Coefficient
DACOUT Load Regulation
Switching Frequency
GATE Maximum On-Time
f
OSC
t
ON
TCV
DACOUT
DAC code = 0F to FF hex, source or sink
50µA
-1
250
300
3
V
FB
TCV
FB
COMP = 1.5V
DAC code = 00 hex
DAC code = FF hex
DAC Code = 01 to FF hex,
DAC guaranteed monotonic
-3
-1
0.0007
+1
340
50
T
A
= +25°C
T
A
= 0°C to +85°C
CS+ = 3V to 100V
Gate high or low, I
GATE
=
±50mA
-25
V
IN
UVLO
I
IN
I
SHDN
00 hex loaded to DAC
Resistance from either pin to ground
0.5
1.80
Both rise/fall, hysteresis = 100mV
2.7
2.1
0.5
25
1
2.00
±0.005
5
10
+25
5.5
2.6
1
65
2.0
2.20
V
V
mA
µA
MΩ
V
%/V
Ω
nA
V
%/°C
200
100
+3
+1
µS
Ω
mV
LSB
%/°C
mV
kHz
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.24375 1.2500 1.25625
1.24250 1.2500 1.25750
0.0007
110
www.maximintegrated.com
Maxim Integrated | 2
MAX1932
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Electrical Characteristics (continued)
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= 0°C to +85°C,
unless otherwise noted.)
PARAMETER
DIGITAL INPUTS (DIN, SCLK,
CS)
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUT (CL)
Output Low Voltage
Output High Voltage
SPI TIMING (FIGURE 5)
SCLK Clock Frequency
SCLK Low Period
SCLK High Period
Data Hold Time
Data Setup Time
CS
Assertion to SCLK
Rising Edge Setup Time
CS
Deassertion to SCLK
Rising Edge Setup Time
SCLK Rising Edge
to
CS
Deassertion
SCLK Rising Edge
to
CS
Assertion
CS
High Period
f
SCLK
t
CL
t
CH
t
DH
t
DS
t
CSS0
t
CSS1
t
CSH1
t
CSH0
t
CSW
125
125
0
125
200
200
200
200
300
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
SINK
= 1mA
I
SOURCE
= 0.5mA
V
IN
- 0.5
0.1
V
V
T
A
= +25°C
T
A
= 0°C to +85°C
-1
10
5
1.4
200
+1
0.6
V
V
mV
µA
nA
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Electrical Characteristics
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= -40°C to +85°C,
unless otherwise noted.) (Note 2)
PARAMETER
GENERAL
Input Supply Range
V
IN
Undervoltage Lockout
Operating Supply Current
V
IN
Shutdown Supply Current
Input Resistance for CS+/CS-
Current-Limit Threshold
for CS+/CS-
Gate-Driver Resistance
FB Input Bias Current
Gate high or low, I
GATE
=
±50mA
-30
V
IN
UVLO
I
IN
I
SHDN
00 hex loaded to DAC
Resistance from either pin to ground
0.5
1.80
Both rise/fall, hysteresis = 100mV
2.7
2.1
5.5
2.6
1
65
2
2.20
10
+30
V
V
mA
µA
MΩ
V
Ω
nA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
www.maximintegrated.com
Maxim Integrated | 3
MAX1932
Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Electrical Characteristics (continued)
(V
IN
= 3.3V,
CS
= SCLK = D
IN
= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2,
T
A
= -40°C to +85°C,
unless otherwise noted.) (Note 2)
PARAMETER
FB Voltage
FB to COMP Transconductance
COMP Pulldown Resistance
in Shutdown
DACOUT to FB Voltage Difference
DACOUT Differential Nonlinearity
(Note 1)
DACOUT Load Regulation
Switching Frequency
DIGITAL INPUTS (DIN, SCLK,
CS)
Input Low Voltage
Input High Voltage
DIGITAL OUTPUT (CL)
Output Low Voltage
Output High Voltage
SPI TIMING (FIGURE 5)
SCLK Clock Frequency
SCLK Low Period
SCLK High Period
Data Hold Time
Data Setup Time
CS
Assertion to SCLK
Rising Edge Setup Time
CS
Deassertion to SCLK
Rising Edge Setup Time
SCLK Rising Edge
to
CS
Deassertion
SCLK Rising Edge
to
CS
Assertion
CS
High Period
f
SCLK
t
CL
t
CH
t
DH
t
DS
t
CSS0
t
CSS1
t
CSH1
t
CSH0
t
CSW
125
125
0
125
200
200
200
200
300
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
SINK
= 1mA
I
SOURCE
= 0.5mA
V
IN
- 0.5
0.1
V
V
1.4
0.6
V
V
f
OSC
SYMBOL
V
FB
COMP = 1.5V
DAC code = 00 hex
DAC code = FF hex
DAC Code = 01 to FF hex, DAC
guaranteed monotonic
DAC code = 0F to FF hex, source or sink
50µA
-4
-1
-1
240
CONDITIONS
MIN
1.23875
50
TYP
MAX
1.26125
200
100
+4
+1
+1
360
UNITS
V
µS
Ω
mV
LSB
mV
kHz
Note 1:
DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2:
Specifications to -40°C are guaranteed by design and not production tested.
FPGA/CPLD
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