74AHC123A-Q100;
74AHCT123A-Q100
Dual retriggerable monostable multivibrator with reset
Rev. 1 — 23 May 2013
Product data sheet
1. General description
The 74AHC123A-Q100; 74AHCT123A-Q100 are high-speed Si-gate CMOS devices and
are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard no. 7A.
The 74AHC123A-Q100; 74AHCT123A-Q100 are dual retriggerable monostable
multivibrators with output pulse width control by three methods. The selection of an
external resistor (R
ext
) and capacitor (C
ext
) program the basic pulse time. The external
resistor and capacitor are normally connected as shown in
Figure 11.
Once triggered, the basic output pulse width may be extended by retriggering the gated
active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating
this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as
desired. Alternatively an output delay can be terminated at any time by a LOW-going edge
on input nRD, which also inhibits the triggering.
An internal connection from nRD to the input gate makes it possible to trigger the circuit by
a positive-going signal at input nRD as shown in
Table 3. Figure 8
and
Figure 9
illustrate
pulse control by retriggering and early reset. The values of the external timing
components R
ext
and C
ext
, determine the basic output pulse width. When C
ext
10 nF, the
typical output pulse width is defined as: t
W
= R
ext
C
ext
where t
W
= pulse width in ns;
R
ext
= external resistor in k; C
ext
= external capacitor in pF. Schmitt-trigger action at all
inputs makes the circuit highly tolerant to slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
CC
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
For 74AHC123A-Q100 only: operates with CMOS input levels
For 74AHCT123A-Q100 only: operates with TTL input levels
ESD protection:
NXP Semiconductors
74AHC123A-Q100; 74AHCT123A-Q100
Dual retriggerable monostable multivibrator with reset
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC123AD-Q100
74AHCT123AD-Q100
74AHC123APW-Q100
74AHCT123APW-Q100
74AHC123ABQ-Q100
74AHCT123ABQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal
SOT763-1
enhanced very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
14
15
CX
RCX
&
13
1
14 1CEXT
6 2CEXT
15 1REXT/CEXT
7 2REXT/CEXT
S
Q
1A 1
2A 9
1B 2
2B 10
T
Q
RD
4 1Q
12 2Q
13 1Q
5 2Q
6
7
2
4
3
R
CX
RCX
&
5
9
10
1RD 3
2RD 11
001aae521
12
11
R
001aae522
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AHC_AHCT123A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
2 of 22
NXP Semiconductors
74AHC123A-Q100; 74AHCT123A-Q100
Dual retriggerable monostable multivibrator with reset
14
15
S
1A
1
T
2
Q
4
Q
1CEXT
1REXT/CEXT
13
1Q
1Q
1B
RD
3
6
7
S
2CEXT
1RD
2REXT/CEXT
2A
9
T
10
Q
5
2Q
Q
12
2Q
2B
RD
11
aaa-000650
2RD
Fig 3. Functional diagram
74AHC_AHCT123A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
3 of 22
NXP Semiconductors
74AHC123A-Q100; 74AHCT123A-Q100
Dual retriggerable monostable multivibrator with reset
nREXT/CEXT
V
CC
Q
RD
Q
V
CC
CL
R
CL
V
CC
R
R
CL
A
CL
CL
B
R
001aae524
For minimum noise generation, ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND).
Fig 4. Functional diagram
74AHC_AHCT123A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
4 of 22
NXP Semiconductors
74AHC123A-Q100; 74AHCT123A-Q100
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO16, TSSOP16
Fig 6. Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
2A
2B
2RD
2Q
1Q
1CEXT
1REXT/CEXT
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
negative-edge triggered input 1
positive-edge triggered input 1
direct reset LOW and positive-edge triggered input 1
active LOW output 1
active HIGH output 2
external capacitor connection 2
external resistor and capacitor connection 2
ground (0 V)
negative-edge triggered input 2
positive-edge triggered input 2
direct reset LOW and positive-edge triggered input 2
active LOW output 2
active HIGH output 1
external capacitor connection 1
external resistor and capacitor connection 1
supply voltage
74AHC_AHCT123A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
5 of 22
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