19-4115; Rev 0; 5/08
EVALUATION KIT AVAILABLE
Low-Jitter Frequency Synthesizer
with Intelligent Dynamic Switching
General Description
The MAX3678 is a low-jitter frequency synthesizer with
intelligent dynamic clock switching optimized for systems
where redundant clock failover switching is needed. It
contains a monolithic phase-locked loop (PLL) that
accepts two reference clock inputs and generates nine
phase-aligned outputs. The device continuously monitors
the signal status for both reference clock inputs. In the
event that the primary clock fails, the PLL automatically
switches to the secondary clock input without generating a
phase bump at the clock outputs, using a glitchless
switchover mechanism. A manual switch mode is also pro-
vided for user-controlled switching. The device features
ultra-low jitter generation of 0.3ps
RMS
(integrated 12kHz to
20MHz) and excellent power-supply noise rejection.
The MAX3678 operates from a single +3.3V supply and
typically consumes 400mW. The operating temperature
range is from 0°C to +85°C, and is available in a 8mm x
8mm, 56-pin TQFN package.
Features
♦
Two Reference Clock Inputs: LVPECL
♦
Nine Phase-Aligned Clock Outputs: LVPECL
♦
Automatic or Manual Dynamic Switching Between
Two Reference Clock Inputs
♦
Input Frequencies: 66.67MHz, 133.33MHz,
266.67MHz, 333.33MHz
♦
Output Frequencies: 66.67MHz, 133.33MHz,
266.67MHz, 333.33MHz
♦
Low-Jitter Generation: 0.3ps
RMS
(12kHz to 20MHz)
♦
Clock Failure Indicator for Both Reference Clocks
♦
♦
♦
♦
External Feedback Provides Zero-Delay Capability
Low Output Skew: 20ps Typical
Typical Power Dissipation: 400mW at +3.3V
Operating Temperature: 0°C to +85°C
MAX3678
Ordering Information
PART
MAX3678UTN+
TEMP RANGE
0°C to +85°C
PIN-PACKAGE
56 TQFN-EP*
Applications
Redundant Clock Distribution in Servers
Low-Jitter Frequency Synthesizer with Intelligent
Dynamic Switching
Frequency Translation
Jitter Cleanup and Frequency Synchronization
Functional Diagram
DM
C
PLL
0.1μF
C
REG
0.22μF
DA
PLL_BYPASS
OUTA_EN
REFCLK0
0
REFCLK0
REFCLK1
1
REFCLK1
DIV M
PFD
66.67MHz
LPF
VCO
2.667GHz
DIV A
1
0
OUTA3
OUTA3
OUTA2
OUTA2
OUTA1
OUTA1
IN0FAIL
IN1FAIL
OUTA0
LOCK
BUSY
CLK_SELECTED
SEL_CLK
DIV B
IDS_MODE
MR
0
INTELLIGENT
DYNAMIC SWITCH
(IDS) CONTROL
DIV N
1
OUTA0
OUTB_EN
OUTB4
OUTB4
OUTB3
OUTB3
OUTB2
1
0
OUTB2
OUTB1
MAX3678
OUTB1
OUTB0
OUTB0
FB_SEL
FB_IN
FB_IN
DB
1
Low-Jitter Frequency Synthesizer with
Intelligent Dynamic Switching
MAX3678
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (V
CC
, VCC_VCO)..............-0.3V to +4.0V
LVPECL Output Current (OUTA[3:0],
OUTA[3 : 0]
, OUTB[4:0],
OUTB[4 : 0]
) .............................-56mA
All Other Pins (REFCLK0,
REFCLK0,
REFCLK1,
REFCLK1, IN0FAIL, IN1FAIL, LOCK, BUSY,
CLK_SELECTED, SEL_CLK, IDS_MODE,
MR,
RSVD, FB_SEL, FB_IN,
FB_IN,
DM, DA, DB,
CPLL, CREG, PLL_BYPASS,
OUTA_EN,
OUTB_EN)
..............................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW
Operating Junction Temperature (T
J
)................-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.)
PARAMETER
Supply Current
POWER-ON RESET
V
CC
Rising
V
CC
Falling
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
IN
= V
CC
V
IN
= GND
I
OH
= -8mA
I
OL
= +8mA
-75
2.4
0.4
V
CC
-
0.7
V
CC
-
2.0
V
CC
-
1.8
0.15
> 40
> 14
1.5
V
IH
= V
CC
- 0.7V, V
IL
= V
CC
- 2.0V
-100
+100
V
CC
-
1.34
1.9
(Note 1)
(Note 1)
2.0
0.8
75
2.55
2.45
V
V
V
V
μA
μA
V
V
SYMBOL
I
CC
CONDITIONS
LVPECL outputs unterminated
MIN
TYP
120
MAX
175
UNITS
mA
LVCMOS/LVTTL INPUTS (MR, SEL_CLK, IDS_MODE, PLL_BYPASS, FB_SEL)
LVCMOS/LVTTL OUTPUTS (CLK_SELECTED,
IN0FAIL, IN1FAIL, BUSY, LOCK)
LVPECL INPUTS (REFCLK0,
REFCLK0,
REFCLK1,
REFCLK1,
FB_IN,
FB_IN)
(Note 2)
Input High Voltage
Input Low Voltage
Input Bias Voltage
Differential-Input Swing
Differential-Input Impedance
Common-Mode Input Impedance
Input Capacitance
Input Current
V
IH
V
IL
V
CMI
V
V
V
V
P-P
k
k
pF
μA
2
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer with
Intelligent Dynamic Switching
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.)
PARAMETER
Input Inrush Current When Power
is Off (Steady State)
Input Inrush Current Overshoot
When Power is Off
Reference Clock Frequency
Reference Clock Frequency
Tolerance
Reference Clock Duty Cycle
Reference Clock Amplitude
Detection Assert Threshold
V
DT
Differential swing (Notes 5, 6, 7)
SYMBOL
I
DC
(Notes 3, 4)
CONDITIONS
MIN
TYP
8
6
MAX
UNITS
mA
mA
MAX3678
I
OVERSHOOT
(Notes 3, 4)
REFERENCE CLOCK INPUTS (REFCLK0,
REFCLK0,
REFCLK1,
REFCLK1)
f
REF
(Note 5)
-25
40
100
200
Table 1
+25
60
400
MHz
ppm
%
mV
P-P
LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 8)
Output High Voltage
Output Low Voltage
Differential-Output Swing
Output Current When Disabled
Output Frequency
Output Rise/Fall Time
Output Duty Cycle
Output-to-Output Skew
PLL Jitter Transfer Bandwidth
Jitter Peaking
PFD Compare Frequency
VCO Center Frequency
Random Jitter Generation
Determinisitic Jitter Caused by
Power-Supply Noise
Phase-Error Detection Window
Rate of Output Period Change
Per Cycle
Output Frequency Transient
Relative to the Initial Lock
Frequency
err
t/cycle
Integrated 12kHz to 20MHz (Notes 5, 6)
(Note 10)
(Notes 5, 11)
±0.5
t
SKEW
f
OUT
t
R
, t
F
20% to 80% (Note 5)
PLL_BYPASS = 0
PLL_BYPASS = 1 (Note 9)
150
48
45
20
55
0.1
66.67
2.667
0.3
5
±0.75
100
±1.0
1.0
V
O
= V
CC
- 2.0V to V
CC
- 0.7V
Tables
2, 3
600
52
55
V
OH
V
OL
V
CC
-
1.13
V
CC
-
1.85
1.1
V
CC
-
0.98
V
CC
-
1.70
1.45
V
CC
-
0.83
V
CC
-
1.55
1.8
130
V
V
V
P-P
μA
MHz
ps
%
%
ps
kHz
dB
MHz
GHz
ps
RMS
ps
P-P
ns
ppm/
cycle
600
ppm
OTHER AC ELECTRICAL SPECIFICATIONS
|
f/f
O
|
During PLL switching (Notes 5, 12)
150
_______________________________________________________________________________________
3
Low-Jitter Frequency Synthesizer with
Intelligent Dynamic Switching
MAX3678
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless
otherwise noted.)
PARAMETER
Frequency Difference Between
Reference Clock and VCO
Within Which the PLL is
Considered in Lock
Frequency Difference Between
Reference Clock and VCO at
Which the PLL is Considered
Out-of-Lock
PLL Lock Time
Master Reset (MR) Minimum
Pulse Width
Propagation Delay from Input to
FB_IN
Propagation Delay from Input to
Any Output
FB_SEL = 1 (Notes 5, 13)
PLL_BYPASS = 1
-100
1.0
t
LOCK
Figure 2
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
500
ppm
800
ppm
400
100
+100
μs
ns
ps
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
See the
Power-On-Reset (POR)
section for more information.
LVPECL inputs can be AC- or DC-coupled.
For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with
V
CC
pins connected to GND. See Figure 1.
Measured with LVPECL input (V
IH
, V
IL
) as specified.
Guaranteed by design and characterization.
Measured using reference clock input with 550ps rise/fall time (20% to 80%).
When input differential swing is below the specified threshold, a clock failure is declared. See Figure 8.
LVPECL outputs terminated 50Ω to V
TT
= V
CC
- 2V.
Measured with 50% duty cycle at reference clock input.
Measured with 50mV
P-P
sinusoidal noise on the power supply, f
NOISE
= 100kHz.
See the
Phase Qualification
section for more information.
This specification is not met when the intelligent dynamic switch (IDS) operation follows that of Case 2b (Figure 4).
Measured using 133.33MHz clock at reference input and feedback input with matched slew rates.
4
_______________________________________________________________________________________
Low-Jitter Frequency Synthesizer with
Intelligent Dynamic Switching
MAX3678
INRUSH CURRENT
(mA)
I
OVERSHOOT
I
DC
t
Figure 1. LVPECL Input Inrush Current
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
PHASE NOISE AT 133.33MHz
MAX3678 toc01
PHASE NOISE AT 266.67MHz
MAX3678 toc02
PHASE NOISE AT 333.33MHz
-70
-80
PHASE NOISE (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
RANDOM JITTER = 0.34ps
RMS
INTEGRATED 12kHz TO 20MHz
MAX3678 toc03
-60
-70
-80
PHASE NOISE (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
RANDOM JITTER = 0.31ps
RMS
INTEGRATED 12kHz TO 20MHz
-60
-70
-80
PHASE NOISE (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
RANDOM JITTER = 0.37ps
RMS
INTEGRATED 12kHz TO 20MHz
-60
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
JITTER TRANSFER
MAX3678 toc04
RANDOM JITTER GENERATION
vs. DIFFERENTIAL-INPUT SWING
MAX3678 toc05
REFERENCE CLOCK AMPLITUDE DETECTION
ASSERT THRESHOLD vs. INPUT FREQUENCY
280
ASSERT THRESHOLD (mV
P-P
)
260
240
220
200
180
160
140
120
100
INPUT RISE/FALL TIME = 270ps
INPUT RISE/FALL TIME = 540ps
MAX3678 toc06
5
0
JITTER TRANSFER (dB)
-5
-10
-15
-20
-25
-30
1k
10k
100k
1.0
RANDOM JITTER GENERATION (ps
RMS
)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
f
OUT
= 133.33MHz
INTEGRATED 12kHz TO 20MHz
MANUAL SWITCH MODE
300
1M
10
100
1000
10,000
50
100
150
200
250
300
350
JITTER FREQUENCY (Hz)
DIFFERENTIAL INPUT SWING (mV
P-P
)
REFERENCE CLOCK INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
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