PTN3355
Low power DisplayPort to VGA adapter with integrated
1 : 2 VGA switch
Rev. 3.1 — 4 November 2016
Product data sheet
1. General description
PTN3355 is a DisplayPort to VGA adapter with an integrated 1 : 2 VGA switch optimized
primarily for motherboard applications, to convert a DisplayPort signal from the chip set to
an analog video signal that directly connects to the VGA connector. PTN3355 integrates a
DisplayPort receiver, a high-speed triple video digital-to-analog converter and 1 : 2 VGA
switch that supports a wide range of display resolutions, for example, VGA to WUXGA
(see
Table 9).
PTN3355 supports either one or two DisplayPort lanes operating at either
2.7 Gbit/s or 1.62 Gbit/s per lane.
PTN3355 supports I
2
C-bus over AUX per
DisplayPort standard
(Ref.
1),
and bridges the
VESA DDC channel to the DisplayPort Interface.
PTN3355 is powered from a 3.3 V power supply and consumes approximately 200 mW of
power for video streaming in WUXGA resolution and 410
W
of power in Low-power
mode. The VGA output is powered down when there is no valid DisplayPort source data
being transmitted. PTN3355 also aids in monitor detection by performing load sensing on
RGB lines and reporting sink connection status to the source.
2. Features and benefits
2.1 VESA-compliant DisplayPort converter
Main Link: 1-lane and 2-lane modes supported
HBR (High Bit Rate) at 2.7 Gbit/s per lane
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
BER (Bit Error Rate) better than 10
9
DisplayPort Link down-spreading supported
1 MHz AUX channel
Supports native AUX CH syntax
Supports I
2
C-bus over AUX CH syntax
Active HIGH Hot Plug Detect (HPD) signal to the source
2.2 VESA-compliant eDP extensions
Supports Alternate Scrambler Seed Reset (ASSR)
Supports Alternate Enhanced Framing mode - Enhanced Framing
NXP Semiconductors
PTN3355
Low power DP to VGA adapter with integrated 1 : 2 VGA switch
2.3 DDC channel output
I
2
C-Over-AUX feature facilitates support of MCCS, DDC/CI, and DDC protocols (see
Ref. 2)
2.4 Analog video output
VSIS 1.2 compliance (Ref.
3)
for supported video output modes
Analog RGB current-source outputs
3.3 V VSYNC and HSYNC outputs
Pixel clock up to 240 MHz
Triple 8-bit Digital-to-Analog Converter (DAC)
Direct drive of double terminated 75
load with standard 700 mV (peak-to-peak)
signals
Integrated 1 : 2 VGA switch
2.5 General features
Supports firmware upgradability through ‘Flash-over-AUX’ scheme for Windows
Supports firmware upgradability through I
2
C-bus interface
Monitor presence detection through load detection scheme. Connection/disconnection
reported via HPD IRQ and DPCD update.
Wide set of display resolutions are supported
1
:
1920
1440, 60 Hz, 18 bpp, 234 MHz pixel clock rate
2048
1152, 60 Hz (reduced blanking), 24 bpp, 162 MHz pixel clock rate
2048
1536, 50 Hz (reduced blanking), 24 bpp, 167.2 MHz pixel clock rate
WUXGA: 1920
1200, 60 Hz, 18 bpp, 193 MHz pixel clock rate
WUXGA: 1920
1200, 60 Hz (reduced blanking), 24 bpp, 154 MHz pixel clock rate
UXGA: 1600
1200, 60 Hz, 162 MHz pixel clock rate
SXGA: 1280
1024, 60 Hz, 108 MHz pixel clock rate
XGA: 1024
768, 60 Hz, 65 MHz pixel clock rate
SVGA: 800
600, 60 Hz, 40 MHz pixel clock rate
VGA: 640
480, 60 Hz, 25 MHz pixel clock rate
Any resolution and refresh rates are supported from 25 MHz up to 180 MHz pixel
clock rate at 24 bpp, or up to 240 MHz pixel clock rate at 18 bpp
Bits per color (bpc) supported
1
6, 8 bits supported
10, 12, 16 bits supported by truncation to 8 MSBs
All VGA colorimetry formats (RGB) supported
Power modes (when the application design is as per
Figure 4)
Active-mode power consumption: ~200 mW at WUXGA, 1920
1200, 60 Hz
(18 bpc)
410
W
at Low-power mode
Supports slave I
2
C-bus interface for host debugging and configuration
1.
Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane
DisplayPort configuration is able to support over 2.7 Gbit/s per lane of DP Main Link.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
PTN3355
Product data sheet
Rev. 3.1 — 4 November 2016
2 of 37
NXP Semiconductors
PTN3355
Low power DP to VGA adapter with integrated 1 : 2 VGA switch
Supports flexible choice of timing reference
On-board oscillator with external crystal, ceramic resonator
Different frequencies supported: 25 MHz, 27 MHz, 33 MHz
ESD protection: 7.5 kV HBM
Single power supply (3.3 V) for easy integration in the platforms
Commercial temperature range: 0
C
to 85
C
40-pin HVQFN, 6 mm
6 mm
0.85 mm (nominal); 0.5 mm pitch; lead-free package
3. Applications
Notebook computers, tablets and desktop PCs
Dongles, adapters, docking stations
4. Ordering information
Table 1.
Ordering information
Topside mark
PTN3355
Package
Name
PTN3355BS
[1]
HVQFN40
HVQFN40
Description
plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; 6
6
0.85 mm
[3]
plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; 6
6
0.85 mm
[3]
Version
SOT618-1
SOT618-1
Type number
PTN3355BS/FX
[2]
PTN3355
[1]
[2]
[3]
PTN3355BS uses latest firmware version.
PTN3355BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).
Maximum height is 1 mm.
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PTN3355BSMP
Package
Packing method
Minimum
order
quantity
Temperature
Type number
PTN3355BS
[1]
HVQFN40
HVQFN40
Reel 13” Q2/T3 *standard mark 4000
SMD dry pack
Reel 13” Q2/T3 *standard mark 4000
SMD dry pack
T
amb
= 0
C
to +85
C
T
amb
= 0
C
to +85
C
PTN3355BS/FX
[2]
PTN3355BS/FXMP
[1]
[2]
PTN3355BS uses latest firmware version.
PTN3355BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).
PTN3355
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3.1 — 4 November 2016
3 of 37
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Product data sheet
Rev. 3.1 — 4 November 2016
4 of 37
PTN3355
5. Functional diagram
NXP Semiconductors
PTN3355
DOCK_IN,
CFG3, CFG5,
TESTMODE
RX PHY
ANALOG
SUBSYSTEM
DIFF CDR,
RCV S2P
RX PHY DIGITAL
DE-SCRAM
ISOCHRONOUS LINK
R[7:0]
INTERFACE DE-SKEWING
G[7:0]
MAIN
STREAM
B[7:0]
H, V
sync
VIDEO DAC SUBSYSTEM
MONITOR
PRESENCE
DETECT
channel 1
DAC
DAC
DAC
RED1
GRN1
BLU1
VGA
OUTPUT
WITH
1:2
VGA
SWITCH
HSYNC1
VSYNC1
RED2
GRN2
BLU2
HSYNC2
VSYNC2
10b/8b
ML0_P, ML0_N
TIME
CONV.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
V
bias
DIFF CDR,
RCV S2P
DE-SCRAM
10b/8b
ML1_P, ML1_N
DPCD
REGISTERS
CONTROL
NVM
MCU
V
bias
RCV
MANCHESTER
CODEC
AUX_P, AUX_N
DRV
AUX COMMAND
LEVEL MODULE
I
2
C-BUS
MASTER
DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA
HPD
V
bias
RX DIGITAL SUBSYSTEM
OSC_IN
OSC_OUT
RSET
RST_N
CFG1_SCL, CFG2_SDA
002aag883
channel 2
TIMING RECOVERY
Low power DP to VGA adapter with integrated 1 : 2 VGA switch
PTN3355
Fig 1.
Functional diagram
NXP Semiconductors
PTN3355
Low power DP to VGA adapter with integrated 1 : 2 VGA switch
6. Pinning information
6.1 Pinning
35 VDDA15_DAC
37 TESTMODE
34 OSC_OUT
36 VDDD15
38 PVDD33
33 OSC_IN
39 SWOUT
40 PGND
32 RED2
terminal 1
index area
VDDA33_DNW
DOCK_IN
AUX_P
AUX_N
VDDE33_IO
ML0_P
ML0_N
VDDA15_DP
ML1_P
1
2
3
4
5
6
7
8
9
31 RED1
30 RSET
29 GRN2
28 GRN1
27 BLU2
26 BLU1
25 HSYNC1
24 VSYNC1
23 DDC_SCL2
22 DDC_SDA1
21 VDDE33_IO
DDC_SCL1 20
002aag884
© NXP Semiconductors N.V. 2016. All rights reserved.
PTN3355BS
GND
(1)
RST_N 11
DDC_SDA2 12
HPD 13
CFG1_SCL 14
CFG5 15
CFG3 16
CFG2_SDA 17
VSYNC2 18
HSYNC2 19
ML1_N 10
Transparent top view
(1) Exposed die pad.
Fig 2.
Pin configuration for HVQFN40
6.2 Pin description
Table 3.
Symbol
VDDA33_DNW
DOCK_IN
AUX_P
AUX_N
VDDE33_IO
ML0_P
ML0_N
VDDA15_DP
ML1_P
Pin description
Pin
1
2
3
4
5
6
7
8
9
Type
power
3.3 V digital I/O
self-biasing differential
input
self-biasing differential
input
power
self-biasing differential
input
self-biasing differential
input
power
self-biasing differential
input
Description
3.3 V power supply
Docked indication signal
DisplayPort AUX channel positive input
DisplayPort AUX channel negative input
3.3 V power supply for I/O
DisplayPort Main Link lane 0 positive input
DisplayPort Main Link lane 0 negative input
1.5 V power supply for DisplayPort PHY; power provided to this pin
from SWOUT pin
DisplayPort Main Link lane 1 positive input
PTN3355
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 3.1 — 4 November 2016
5 of 37
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