Drives either a 50-ohm or 75-ohm transmission line
Over voltage tolerant input hot swappable
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
High-speed operation > 200 MHz
LVTTL-/LVCMOS-compatible input
— Output disable to three-state
• Industrial versions available
• Packages available include: SOIC/SSOP
•
•
•
•
•
•
•
•
•
•
•
Description
The Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1810 fanout buffer features one input and
ten three-state outputs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance-matching and eliminate the need for series-
damping resistors; they also reduce noise overall.
Block Diagram
Q1
OE#
Q2
Q3
Q4
Q5
IN
Q6
Q7
Q8
Q9
Q 10
OUTPUT
(AVCMOS)
Pin Configuration
VDD
GND
Q10
VDD
Q9
OE#
IN
GND
GND
Q8
VDD
Q7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CY2CC1810
GND
Q1
VDD
Q2
GND
Q3
Q4
GND
Q5
VDD
Q6
GND
GND
24 pin SOIC/SSOP
Pin Description
Pin Number
1,7,8,12,13,17,20,24
3,10,15,22
5
6
2,4,9,11,14,16,18,19,21,23
Pin Name
G
ND
V
DD
OE#
IN
Q10........Q1
Ground
Power Supply
Output Enable
Input
Output
Pin Description
Power
Power
LVTTL/LVCMOS
LVTTL/LVCMOS
AVCMOS
Cypress Semiconductor Corporation
Document #: 38-07055 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
COMLINK™ SERIES
CY2CC1810
Maximum Ratings
[1][2]
Storage Temperature: ................................–65°C to + 150°C
Ambient Temperature:................................... –40°C to +85°C
Supply Voltage to Ground Potential
V
CC
.................................................................. –0.5V to 4.6V
Input ................................................................. –0.5V to 5.8V
Supply Voltage to Ground Potential
(Outputs only) ........................................ –0.5V to V
DD
+ 0.5V
DC Output Voltage................................. –0.5V to V
DD
+ 0.5V
Power Dissipation........................................................ 0.75W
DC Parameter
@ 3.3V V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C (see
Figure 6)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OK
O
OFF
V
H
Description
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Continuous Clamp Current
Power-down Disable
Input Hysteresis
Conditions
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
= V
IH
or V
IL
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
DD
= Max.
V
DD
= Max.
V
DD
= Max., V
IN
=
V
DD
(Max)
V
DD
= Min., I
IN
= –18 mA
V
DD
= Max., V
OUT
= GND
V
DD
=
GND
,
V
OUT
= < 4.5V
80
–0.7
V
IN
= 2.7V
V
IN
= 0.5V
I
OH
= –12 mA
I
OL
= 12 mA
2
Min.
2.3
Typ.
3.3
0.2
0.5
5.8
0.8
1
–1
20
–1.2
–50
100
Max.
Unit
V
V
V
V
uA
uA
uA
V
mA
uA
mV
DC Parameter
@ 2.5V V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C (see
Figure 1)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OK
O
OFF
V
H
Description
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Continuous Clamp Current
Power-down Disable
Input Hysteresis
Conditions
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
= V
IH
or V
IL
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
DD
= Max.
V
DD
= Max.
V
DD
= Max., V
IN
= V
DD
(Max.)
V
DD
= Min., I
IN
= –18 mA
V
DD
= Max., V
OUT
= GND
V
DD
= GND, V
OUT
= < 4.5V
80
–0.7
V
IN
= 2.4V
V
IN
= 0.5V
I
OH
= –7 mA
I
OH
= 12 mA
I
OL
= 12 mA
1.6
Min.
1.8
1.6
0.65
5.0
0.8
1
–1
20
–1.2
–50
100
Typ.
Max.
Unit
V
V
V
V
V
uA
uA
uA
V
mA
uA
mV
Capacitance
Symbol
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
2.5
6.5
Max.
Unit
pF
pF
Note:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07055 Rev. *C
Page 2 of 8
COMLINK™ SERIES
CY2CC1810
Power Supply Characteristics
(See
Figure 1)
Parameter
∆
ICC
I
CCD
Description
Delta I
CC
Quiescent
Power Supply Current
Dynamic Power Supply
Current
Total Power Supply
Current
Test Conditions
(I
DD
@ V
DD
= Max. and V
IN
= V
DD
) – (I
DD
@ V
DD
=
Max. and V
IN
= V
DD
– 0.6V)
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open fL = 40 MHz
fL= fMAX
OE# = V
DD
fL=100 MHz
OE# = GND
Min.
Typ.
Max.
50
Unit
uA
mA/
MHz
mA
0.63
I
C
25
High-frequency Parametrics
Parameter
D
J
Description
Jitter, Deterministic
Test Conditions
50% duty cycle tW(50–50)
The “point to point load circuit”
|Output Jitter – Input Jitter|
50% duty cycle tW(50–50)
Standard Load Circuit.
50% duty cycle tW(50–50)
The “point to point load circuit”
F
max(20)
Maximum frequency
V
DD
= 3.3 V
Maximum frequency
V
DD
= 2.5 V
t
W
Minimum pulse
V
DD
= 3.3 V
Minimum pulse
V
DD
= 2.5 V
20% duty cycle tW(20–80)
The “point to point load circuit”
V
IN
= 3.0V/0.0V V
OUT
= 2.3V/0.4V
The “point to point load circuit”
V
IN
= 2.4V/0.0V V
OUT
= 1.7V/0.7V
The “point to point load circuit”
V
IN
= 3.0V/0.0V F = 100 MHz
V
OUT
= 2.0V/0.8V
The “point to point load circuit”
V
IN
= 2.4V/0.0V F = 100 MHz
V
OUT
= 1.7V/0.7V
See
Figure 8
Min.
Typ
Max
20
Unit
ps
F
max
Maximum frequency
V
DD
= 3.3V
See
Figure 6
See
Figure 8
See
Figure 8
160
200
200
MHz
MHz
See
Figure 3
See
Figure 7
2
100
ns
See
Figure 2
1
AC Switching Characteristics
@ 3.3V V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C (See
Figure 6)
Parameter
t
PLH
t
PHL
t
PHZ
t
PLZ
t
R
t
F
t
SK(0)
t
SK(p)
t
SK(t)
t
OFF
t
ON
Propagation Delay – Low to High
Propagation Delay – High to Low
Propagation Delay – High to High Z
Propagation Delay – Low to High Z
Output Rise Time
Output Fall Time
Output Skew: Skew between outputs of the same package (in
phase)
See
Figure 12
See
Figure 9
See
Figure 10
Description
See
Figure 9
Min.
1.5
1.5
Typ.
3
3
4
3
0.8
0.8
0.2
0.2
0.3
4.0
4.0
Max.
3.9
3.9
Unit
nS
nS
nS
nS
V/nS
V/nS
nS
nS
nS
nS
nS
Pulse Skew: Skew between opposite transitions of the same output See
Figure 11
(t
PHL
– t
PLH
)
Package Skew: Skew between outputs of different packages at the See
Figure 13
same power supply voltage, temperature and package type.
Delay from OE to Driver Off
Delay from OE to Driver on
Document #: 38-07055 Rev. *C
Page 3 of 8
COMLINK™ SERIES
CY2CC1810
AC Switching Characteristics
@ 2.5V V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C (See
Figure 1)
Parameter
t
PLH
t
PHL
t
PHZ
t
PLZ
t
R
t
F
t
SK(0)
t
SK(p)
t
SK(t)
t
OFF
t
ON
Propagation Delay – Low to High
Propagation Delay – High to Low
Propagation Delay – High to High Z
Propagation Delay – Low to High Z
Output Rise Time
Output Fall Time
Output Skew: Skew between outputs of the same package (in phase) See
Figure 12
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
– t
PLH
)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
Delay from OE to Driver Off
Delay from OE to Driver on
See
Figure 11
See
Figure 13
See
Figure 4
See
Figure 5
Description
See
Figure 4
Min.
1.5
1.5
Typ.
3.8
3.8
5
4
0.4
0.6
0.2
0.2
0.3
5.0
5.0
Max. Unit
3.5
3.5
nS
nS
nS
nS
V/nS
V/nS
nS
nS
nS
nS
nS
Parameter Measurement Information: V
DD
@ 2.5V
[3,5,6
]
500 ohm
From O utput
Under Test
C
L
= 50 pF
500 ohm
2x VDD
Open
V
SS
Input
t
PLH
Output
1.25 V
1.25 V
t
PHL
1.25 V
2.5 V
0V
V
OH
1.25 V
V
OL
2.5 V
VOL
(max)
Figure 4. Voltage Waveforms–Propagation Delay Times
[9]
VOH (min)
Figure 1. Load Circuit
Output Control
(low-level enabling)
1.25 V
0V
t
PLZ
1.25 V
V
OL
+ 0.3V
t
PHZ
1.25V
V
OH
- 0.3V
t
w(50-50)
Input
1.25 V
t
w(20-80)
Input
1.25 V
1.25 V
2.5 V
0V
2.5 V
0V
Waveform 2
S1 at GND
Waveform 1
S1 at 2 x VDD
t
PZL
Z
2.5 V
V
OL
V
OH
~0 V
t
PZH
Z
Figure 2. Voltage Waveforms–Pulse Duration
From Output
Under Test
C
L
= 3 pF
500 ohm
Figure 5. Voltage Waveforms–
Enable and Disable Times
[4,7,8]
Table 1.
Test
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
2 × V
DD
V
SS
See
Figure 4
See
Figure 5
Figure 3. Point-to-Point Load Circuit
Notes:
3. C
L
includes probe and jig capacitance.
4. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH except when disabled by the output control.
5. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, t
R
< 2.5 nS, t
F
< 2.5 nS.
6. Outputs are measured one at a time with one transition per measurement.
7. t
PLZ
and t
PHZ
are the same as t
DIS
.
8. t
PZL
and t
PZH
are the same as t
EN
.
9. t
PLH
and t
PHL
are the same as t
PD
.
Document #: 38-07055 Rev. *C
Page 4 of 8
COMLINK™ SERIES
CY2CC1810
Parameter Measurement Information
:
V
DD
@ 3.3V
[10,12,13]
500 ohm
From Output
Under Test
C
L
= 50 pF
500 ohm
Output
2x VDD
Open
V
SS
Input
t
PLH
1.5 V
1.5 V
t
PHL
1.5 V
1.5 V
0V
V
OH
1.5 V
V
OL
Figure 9. Voltage Waveforms–
Propagation Delay Times
[16]
Figure 6. Load Circuit
VOH (min)
3.3 V
VOL
(max)
t
w(50-50)
Input
1.5 V
t
w(20-80)
Input
1.5 V
1.5 V
2.7 V
0V
2.7 V
0V
Output Control
(low-level enabling)
t
PZL
Waveform 1
S1 at 2 x VDD
Z
1.5 V
0V
t
PLZ
1.5 V
V
OL
+ 0.3V
t
PHZ
1.5V
V
OH
- 0.3V
3V
V
OL
V
OH
~0 V
t
PZH
Waveform 2
S1 at GND
Z
Figure 7. Voltage Waveforms–Pulse Duration
From Output
Under Test
C
L
= 3 pF
500 ohm
Figure 10. Voltage Waveforms–
Enable and Disable Times
[11,14,15]
Table 2.
Test
S1
Open
2xVDD
VSS
See
Figure 9
See
Figure 10
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Figure 8. Point-to-Point Load Circuit
3V
1.5V
INPUT
t
PLH
t
PHL
0V
VOH
1.5V
OUTPUT
tsk
(P)
=
VOL
l
t
PHL
- t
PLH
l
Figure 11. Pulse Skew–tsk
(p)
Notes:
10. C
L
includes probe and jig capacitance
11. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH, except when disabled by the output control.
12. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, t
R
< 2.5 nS, t
F
< 2.5 nS.
13. The outputs are measured one at a time with one transition per measurement.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
