PTN3300A
DVI/HDMI level shifter with inverting 1.1 V HPD
Rev. 01 — 30 June 2008
Product data sheet
1. General description
The PTN3300A is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI and HDMI compliant open-drain
current-steering differential output signals, up to 2.25 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50
Ω
to 3.3 V on the sink side. Additionally, the
PTN3300A provides a single-ended active inverting buffer for voltage translation of the
HPD signal from 5 V on the sink side to 1.1 V on the source side and provides a channel
for level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V
source-side and 5 V sink-side. The DDC channel is implemented using pass gate
technology allowing level shifting as well as disablement (isolation between source and
sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3300A typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0
specification or HDMI v1.3a specification. By using PTN3300A, chip set vendors are able
to implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See
Figure 1.
The PTN3300A main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of
DisplayPort
Standard v1.1
and/or
PCI Express Standard v1.1,
and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI V1.3a electrical specifications. The
PTN3300A also supports power-saving modes in order to minimize current consumption
when no display is active or connected.
The PTN3300A supports level translation functions and features supporting DVI and
HDMI. It is identical to the PTN3300B except that the HPD_SOURCE_N output is the
logic inverse function of input HPD_SINK, level shifted to 1.1 V. For a fully-featured
HDMI/DVI level shifter function that supports active buffering of the DDC lines and HDMI
dongle detect, the PTN3301 should be used.
PTN3300A is powered from a single 3.3 V power supply consuming a small amount of
power (120 mW typ.) and is offered in two different 48-terminal HWQFN packages, one
laminate based (no terminals visible from edge of the package), and one leadframe-based
(terminals visible from edge of the package).
NXP Semiconductors
PTN3300A
DVI/HDMI level shifter with inverting 1.1 V HPD
2. Features
2.1 High-speed TMDS level shifting
I
Converts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI
compliant open-drain current-steering differential output signals
I
TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)
I
Integrated 50
Ω
termination resistors for self-biasing differential inputs
I
Back-current safe outputs to disallow current when device power is off and monitor is
on
I
Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
I
Integrated DDC level shifting (3.3 V source to 5 V sink side)
I
0 Hz to 400 kHz clock frequency
I
Back-power safe to disallow backdrive current when power is off or when DDC is not
enabled
2.3 HPD level shifting
I
HPD
inverting
level shift from 0 V on the sink side to 1.1 V on the source side, or from
5 V on the sink side to 0 V on the source side
I
Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
2.4 General
I
Power supply 3.3 V
±
10 %
I
ESD resilience to 3.5 kV HBM, 1 kV CDM
I
Power-saving modes by source-side disablement (using output enable) as well as
sink-side detection (using HPD)
I
Back-current-safe design on all sink-side terminals
I
Transparent operation: no re-timing or software configuration required
3. Ordering information
Table 1.
Ordering information
Package
Name
PTN3300AHF
PTN3300AHF2
HWQFN48R
HWQFN48
Description
plastic thermal enhanced very very thin quad flat package; no leads;
48 terminals; resin based; body 7
×
7
×
0.7 mm
plastic thermal enhanced very very thin quad flat package; no leads;
48 terminals; body 7
×
7
×
0.65 mm
Version
SOT1031-2
SOT1074-1
Type number
PTN3300A_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 30 June 2008
3 of 23
NXP Semiconductors
PTN3300A
DVI/HDMI level shifter with inverting 1.1 V HPD
5. Pinning information
5.1 Pinning
IN_D4+
IN_D3+
IN_D2+
IN_D1+
IN_D4−
IN_D3−
IN_D2−
IN_D1−
38
GND
terminal 1
index area
GND
V
DD
n.c.
n.c.
GND
REXT
HPD_SOURCE_N
SDA_SOURCE
SCL_SOURCE
n.c.
V
DD
GND
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
37
36
35
34
33
32
GND
V
DD
V
DD
GND
n.c.
n.c.
V
DD
DDC_EN
GND
HPD_SINK
SDA_SINK
SCL_SINK
GND
V
DD
OE_N
PTN3300AHF
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
OUT_D1−
OUT_D4−
OUT_D3−
OUT_D4+
OUT_D3+
OUT_D2+
OUT_D2−
V
DD
V
DD
OUT_D1+
GND
GND
24
002aad647
Transparent top view
HWQFN48R package supply ground is connected to both GND pins and exposed center pad.
GND pins must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the PCB in the thermal pad region.
Fig 3.
Pin configuration for HWQFN48R
PTN3300A_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 30 June 2008
5 of 23
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