74LV164-Q100
8-bit serial-in/parallel-out shift register
Rev. 2 — 18 September 2014
Product data sheet
1. General description
The 74LV164-Q100 is a low-voltage, Si-gate CMOS device and is pin and function
compatible with the 74HC164-Q100 and 74HCT164-Q100.
The 74LV164-Q100 is an 8-bit edge-triggered shift register with serial data entry and an
output from each of the eight stages. Data is entered serially through one of two inputs
(DSA or DSB). Either input can be used as an active HIGH enable for data entry through
the other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP).
It enters Q0, which is the logical AND-function of the two data inputs (DSA and DSB).
Data inputs DSA and DSB, existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
C
Gated serial data inputs
Asynchronous master reset
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74LV164-Q100
8-bit serial-in/parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LV164D-Q100
40 C
to +125
C
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
74LV164PW-Q100
40 C
to +125
C
74LV164BQ-Q100
40 C
to +125
C
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LV164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 18 September 2014
2 of 19
NXP Semiconductors
74LV164-Q100
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0
Q1
Q2
Q3
GND
CP
MR
Q4
Q5
Q6
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input SA
data input SB
output 0
output 1
output 2
output 3
ground (0 V)
clock input (edge triggered LOW-to-HIGH)
master reset input (active LOW)
output 4
output 5
output 6
output 7
supply voltage
74LV164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 18 September 2014
3 of 19
NXP Semiconductors
74LV164-Q100
8-bit serial-in/parallel-out shift register
6. Functional description
Table 3.
Function table
[1]
Input
MR
Reset (clear)
Shift
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition.
Operating mode
Output
CP
X
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
output source or sink current,
V
O
= 0.5 V to (V
CC
+ 0.5 V)
[1]
Min
0.5
-
-
-
-
-
65
Max
+7.0
20
50
25
50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
TSSOP14 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
DHVQFN14 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
74LV164_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 18 September 2014
4 of 19
NXP Semiconductors
74LV164-Q100
8-bit serial-in/parallel-out shift register
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t
r
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
rise time
in free air
input
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
t
f
fall time
input
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
[1]
Min
1.0
0
0
40
-
-
-
-
-
-
-
-
Typ
3.3
-
-
-
-
-
-
-
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
500
200
100
50
Unit
V
V
V
C
ns/V
ns/V
ns/V
ns/V
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V. LV devices are guaranteed to function down to V
CC
= 1.0 V
(with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +85
C
[1]
V
IH
HIGH-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
l
O
=
100 A;
V
CC
= 1.2 V
l
O
=
100 A;
V
CC
= 2.0 V
l
O
=
100 A;
V
CC
= 2.7 V
l
O
=
100 A;
V
CC
= 3.0 V
l
O
=
6
mA; V
CC
= 3.0 V
l
O
=
100 A;
V
CC
= 4.5 V
l
O
=
12
mA; V
CC
= 4.5 V
74LV164_Q100
All information provided in this document is subject to legal disclaimers.
Conditions
Min
0.9
1.4
2.0
-
-
-
-
-
1.8
2.5
2.8
2.4
4.3
3.6
Typ
-
-
-
-
-
-
-
1.2
2.0
2.7
3.0
2.82
4.5
4.2
Max
-
-
-
-
0.3
0.6
0.8
Unit
V
V
V
V
V
V
V
0.7
V
CC
-
0.3
V
CC
V
-
-
-
-
-
-
-
V
V
V
V
V
V
V
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 18 September 2014
5 of 19
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
