Low Skew, 1-to-12 Differential-to-
LVCMOS Fanout Buffer
83948I-01
Data Sheet
G
ENERAL
D
ESCRIPTION
The 83948I-01 is a low skew, 1-to-12 Differential-
t o - LV C M O S Fa n o u t B u f f e r. T h e 8 3 9 4 8 I - 0 1 h a s
two selectable clock inputs. The CLK, nCLK pair can accept
most standard differential input levels. The LVCMOS_CLK
can accept LVCMOS or LVTTL input levels. The low
impedance LVCMOS outputs are designed to drive 50
series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
The 83948I-01 is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics
make the 83948I-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
•
Twelve LVCMOS outputs
•
Selectable LVCMOS clock or differential CLK, nCLK inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 150MHz
•
Output skew: 350ps (maximum)
•
Part to part skew: 1.5ns (maximum)
•
3.3V core, 3.3V output
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
V
DDO
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q11
V
DDO
Q10
GND
Q9
V
DDO
Q8
GND
GND
Q0
Q1
Q2
Q3
24
23
22
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
32 31 30 29 28 27 26 25
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
ICS83948I-01
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 18, 2016
83948I-01 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
10, 14, 18, 22, 26, 30
Name
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
V
DDO
Input
Input
Input
Input
Input
Input
Power
Power
Output
Power
Type
Pullup
Pullup
Pullup
Pullup
Pullup
Description
Clock select input. Selects LVCMOS clock input
when HIGH. Selects CLK, nCLK inputs when LOW.
LVCMOS / LVTTL interface levels.
Clock input. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Clock enable. LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Core supply pin.
Power supply ground.
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins.
Pulldown Inverting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
25
51
51
7
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
pF
KΩ
KΩ
Ω
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
CLK, nCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
—
—
—
—
—
—
0
1
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
—
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
—
—
Outputs
Q0:Q12
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
Non Inverting
Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
©2016 Integrated Device Technology, Inc
2
Revision A March 18, 2016
83948I-01 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, Tstg
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°
TO
85°
Symbol
V
DD
V
DDO
I
DD
Parameter
Input Supply Voltage
Output Supply Voltage
Quiescent Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.6
3.6
55
Units
V
V
mA
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°
TO
85°
Symbol
V
IH
V
IL
V
PP
V
CMR
I
IN
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
Input Current
Output High Voltage
Output Low Voltage
I
OH
= -20mA
I
OL
= 20mA
2.5
0.4
LVCMOS/LVTTL
LVCMOS/LVTTL
CLK, nCLK
CLK, nCLK
0.15
GND + 0.5
Test Conditions
Minimum
2
Typical
Maximum
3.6
0.8
1.3
V
DD
- 0.85
±100
Units
V
V
V
V
µA
V
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
3
Revision A March 18, 2016
83948I-01 Data Sheet
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°
TO
85°
Symbol
f
MAX
t
PD
Parameter
Maximum Output Frequency
CLK, nCLK;
NOTE 1A
Propagation Delay
LVCMOS_CLK;
NOTE 1B
Output Skew; NOTE 2, 6
Part-to-Part Skew;
NOTE 3, 6
Output Rise Time
Output Fall Time
Output Pulse Width
Output Disable Time; NOTE 4
Output Enable Time; NOTE 4
Clock Enable
Setup Time;
NOTE 5
Clock Enable
Hold Time;
NOTE 5
CLK_EN to CLK
CLK_EN to LVC-
MOS_CLK
CLK to CLK_EN
1
0
0
CLK, nCLK
LVCMOS_CLK
Test Conditions
Minimum
150
2.5
3
Measured on
rising edge @V
DDO
/2
Measured on
rising edge @V
DDO
/2
0.8V to 2V
0.8V to 2V
0.2
0.2
tPeriod/2 - 800
Typical
Maximum
Units
MHz
ns
ns
ps
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
6.5
5.5
350
1.5
2
1.0
1.0
tPeriod/2 + 800
11
11
tsk(o)
tsk(pp)
t
R
t
F
t
PW
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
S
t
H
LVCMOS_CLK
1
to CLK_EN
NOTE 1A: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 1B: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the falling edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
4
Revision A March 18, 2016
83948I-01 Data Sheet
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
©2016 Integrated Device Technology, Inc
5
Revision A March 18, 2016
编程基础
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
