PTN3360D
Enhanced performance HDMI/DVI level shifter with active DDC
buffer, supporting 3 Gbit/s operation
Rev. 4 — 29 June 2012
Product data sheet
1. General description
The PTN3360D is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain
current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit
deep color mode, 4K
2K video format or 3D video data transport. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50
to 3.3 V on the sink side. Additionally, the
PTN3360D provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I
2
C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3360D typically come from
a display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3360D, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See
Figure 1.
The PTN3360D main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of
DisplayPort
Standard v1.2
and/or
PCI Express Standard v1.1,
and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The
I
2
C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. The PTN3360D also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
The PTN3360D is a fully featured HDMI as well as DVI level shifter. The PTN3360D
supersedes PTN3360B, and provides a better high speed performance with a
programmable equalizer.
PTN3360D is powered from a single 3.3 V power supply consuming a small amount of
power (230 mW typical) and is offered in a 48-terminal HVQFN48 package.
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
MULTI-MODE DISPLAY SOURCE
OE_N
reconfigurable I/Os
PCIe PHY ELECTRICAL
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
clock
pattern
PCIe
output buffer
TX
FF
TX
AC-coupled
differential pair
clock
CLOCK LANE
OUT_D1+
OUT_D1−
IN_D1+
IN_D1−
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D2+
IN_D2−
OUT_D2+
OUT_D2−
AC-coupled
differential pair
TMDS data
IN_D3+
DATA LANE
IN_D3−
OUT_D3+
OUT_D3−
AC-coupled
differential pair
TMDS data
IN_D4+
DATA LANE
IN_D4−
OUT_D4+
OUT_D4−
PTN3360D
0 V to 3.3 V
quinary input
3.3 V
3.3 V
HPD_SOURCE
EQ5
DDC_EN
(0 V to 3.3 V)
HPD_SINK
0 V to 5 V
5V
SCL_SOURCE
3.3 V
DDC I/O
(I
2
C-bus)
CONFIGURATION
SDA_SOURCE
SCL_SINK
5V
SDA_SINK
002aaf240
Remark:
TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3360D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 29 June 2012
DVI/HDMI CONNECTOR
2 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
2. Features and benefits
2.1 High-speed TMDS level shifting
Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals
TMDS level shifting operation up to 3.0 Gbit/s per lane (300 MHz character clock)
supporting 4K
2K and 3D video formats
Programmable equalizer
Integrated 50
termination resistors for self-biasing differential inputs
Back-current safe outputs to disallow current when device power is off and monitor is
on
Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
Rise time accelerator on sink-side DDC ports
0 Hz to 400 kHz I
2
C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting
HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General
Power supply 3.0 V to 3.6 V
ESD resilience to 6 kV HBM, 1 kV CDM
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required
48-terminal HVQFN48 package
3. Applications
PC motherboard/graphics card
Docking station
DisplayPort to HDMI adapters supporting 4K
2K and 3D video formats
DisplayPort to DVI adapters required to drive long cables
PTN3360D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 29 June 2012
3 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
4. Ordering information
Table 1.
Ordering information
Topside mark
PTN3360DBS
Package
Name
PTN3360DBS
HVQFN48
Description
plastic thermal enhanced very thin quad flat package;
no leads; 48 terminals; body 7
7
0.85 mm
Version
SOT619-1
Type number
5. Functional diagram
OE_N
input bias
enable
50
Ω
50
Ω
PTN3360D
OUT_D4+
OUT_D4−
IN_D4+
IN_D4−
input bias
EQ
enable
enable
50
Ω
50
Ω
OUT_D3+
OUT_D3−
IN_D3+
IN_D3−
input bias
EQ
enable
enable
50
Ω
50
Ω
OUT_D2+
OUT_D2−
IN_D2+
IN_D2−
input bias
EQ
enable
enable
50
Ω
50
Ω
OUT_D1+
OUT_D1−
IN_D1+
IN_D1−
EQ5
HPD_SOURCE
(0 V to 3.3 V)
DDC_EN (0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
EQ
enable
HPD level shifter
200 kΩ
HPD_SINK
(0 V to 5 V)
DDC BUFFER
AND
LEVEL SHIFTER
002aaf241
SCL_SINK
SDA_SINK
Fig 2.
Functional diagram of PTN3360D
PTN3360D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 29 June 2012
4 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
6. Pinning information
6.1 Pinning
48 IN_D4+
45 IN_D3+
42 IN_D2+
39 IN_D1+
47 IN_D4−
44 IN_D3−
41 IN_D2−
38 IN_D1−
43 GND
terminal 1
index area
GND
V
DD
EQ5
n.c.
GND
REXT
HPD_SOURCE
SDA_SOURCE
SCL_SOURCE
1
2
3
4
5
6
7
8
9
37 GND
36 GND
35 n.c.
34 n.c.
33 V
DD
32 DDC_EN
31 GND
30 HPD_SINK
29 SDA_SINK
28 SCL_SINK
27 GND
26 V
DD
25 OE_N
GND 24
002aaf242
46 V
DD
PTN3360DBS
n.c. 10
V
DD
11
GND 12
OUT_D4+ 13
OUT_D4− 14
V
DD
15
OUT_D3+ 16
OUT_D3− 17
GND 18
OUT_D2+ 19
OUT_D2− 20
V
DD
21
OUT_D1+ 22
OUT_D1− 23
Transparent top view
HVQFN48 package supply ground is connected to both GND pins and exposed center pad.
GND pins and the exposed center pad must be connected to supply ground for proper device
operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs
to be soldered to the board using a corresponding thermal pad on the board and for proper heat
conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad
region.
Fig 3.
Pin configuration for HVQFN48
PTN3360D
All information provided in this document is subject to legal disclaimers.
40 V
DD
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 29 June 2012
5 of 24
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