电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

74ALVT16501DG

产品描述Bus Transceivers 2.5/3.3V 18-BIT UNIVERSAL XCVR
产品类别半导体    逻辑   
文件大小103KB,共21页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
下载文档 详细参数 选型对比 全文预览

74ALVT16501DG在线购买

供应商 器件名称 价格 最低购买 库存  
74ALVT16501DG - - 点击查看 点击购买

74ALVT16501DG概述

Bus Transceivers 2.5/3.3V 18-BIT UNIVERSAL XCVR

74ALVT16501DG规格参数

参数名称属性值
产品种类
Product Category
Bus Transceivers
制造商
Manufacturer
NXP(恩智浦)
RoHSDetails
Logic FamilyALVT
Input LevelCMOS
Output LevelLVTTL
输出类型
Output Type
3-State
High Level Output Current- 32 mA
Low Level Output Current64 mA
传播延迟时间
Propagation Delay Time
3 ns
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
2.3 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
封装 / 箱体
Package / Case
TSSOP-56
系列
Packaging
Tube
FunctionUniversal Bus Transceiver
高度
Height
1.05 mm
长度
Length
14.1 mm
安装风格
Mounting Style
SMD/SMT
Number of Channels18
Number of Circuits1
工作电源电压
Operating Supply Voltage
2.5 V, 3.3 V
PolarityNon-Inverting
产品
Product
BiCMOS
Quiescent Current3.5 mA
工厂包装数量
Factory Pack Quantity
35
Supply Current - Max5 mA
Triggering TypePositive Edge
宽度
Width
6.2 mm
单位重量
Unit Weight
0.026103 oz

文档预览

下载PDF文档
74ALVT16501
18-bit universal bus transceiver; 3-state
Rev. 04 — 8 August 2005
Product data sheet
1. General description
The 74ALVT16501 is a high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) product designed for V
CC
operation at 2.5 V and 3.3 V with
I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the
outputs are in the high-impedance state.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
s
18-bit bidirectional bus interface
5 V I/O compatible
3-state buffers
Output capability: +64 mA to
−32
mA
TTL and LVTTL input and output switching levels
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Positive-edge triggered clock inputs
Latch-up protection:
x
JESD78: exceeds 500 mA
ESD protection:
x
MIL STD 883, method 3015: exceeds 2000 V
x
Machine model: exceeds 400 V

74ALVT16501DG相似产品对比

74ALVT16501DG 74ALVT16501DG-T 74ALVT16501DL-T CSC12A03390RGDA
描述 Bus Transceivers 2.5/3.3V 18-BIT UNIVERSAL XCVR Bus Transceivers 2.5/3.3V 18-BIT UNIVERSAL XCVR Bus Transceivers 2.5/3.3V 18-BIT UNIVERSAL XCVR Array/Network Resistor, Isolated, Metal Glaze/thick Film, 0.3W, 390ohm, 100V, 2% +/-Tol, -100,100ppm/Cel,
Reach Compliance Code - unknown unknown compliant
系列 - ALVT ALVT CSC
端子数量 - 56 56 12
最高工作温度 - 85 °C 85 °C 125 °C
最低工作温度 - -40 °C -40 °C -55 °C
封装形式 - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SIP
技术 - BICMOS BICMOS METAL GLAZE/THICK FILM

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2037  1769  135  799  2325  23  39  40  59  21 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved