End of Life. Last Available Purchase Date is 31-Dec-2014
Si9112
Vishay Siliconix
High-Voltage Switchmode Controller
FEATURES
9- to 80-V Input Range
Current-Mode Control
High-Speed, Source-Sink Output Drive
High Efficiency Operation (> 80%)
Internal Start-Up Circuit
Internal Oscillator (1 MHz)
SHUTDOWN and RESET
DESCRIPTION
The Si9112 is a BiC/DMOS integrated circuit designed for use
in high-efficiency switchmode power converters. A
high-voltage DMOS input allows this controller to work over a
wide range of input voltages (9- to 80-VDC). Current-mode
PWM control circuitry is implemented in CMOS to reduce
internal power consumption to less than 10 mW.
A CMOS output driver provides high-speed switching of
MOSPOWER devices large enough to supply 50 W of output
power. When combined with an output MOSFET and
transformer, the Si9112 can be used to implement
single-ended power converter topologies (i.e., flyback,
forward, and cuk).
The Si9112 is available in both standard and lead (Pb)-free
14-pin plastic DIP and SOIC packages which are specified to
operate over the industrial temperature range of −40 C to
85 C.
FUNCTIONAL BLOCK DIAGRAM
OSC
IN
8
OSC
OUT
7
FB
14
COMP
13
DISCHARGE
9
Error
Amplifier
10
−
+
4 V (2%)
Ref
Gen
2V
−
+
+
−
1
BIAS
6
Current
Sources
To
Internal
Circuits
1.2 V
C/L
Comparator
Current-Mode
Comparator
OSC
Clock (
1
/
2
f
OSC
)
V
REF
To
V
CC
4
R
Q
S
5
OUTPUT
−V
IN
3
V
CC
SENSE
V
CC
+V
IN
2
8.1 V
−
+
8.7 V
−
+
Undervoltage Comparator
Q
S
R
11
12
SHUTDOWN
RESET
Pre-Regulator/Start-Up
Applications information, see AN703.
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
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1
Si9112
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to
−V
IN
(V
CC
< +V
IN
+ 0.3 V)
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
+V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 V
Logic Inputs
(RESET, SHUTDOWN, OSC IN) . . . . . . . . . . . . . . . . .
−0.3
V to V
CC
+ 0.3 V
Linear Inputs (FEEDBACK, SENSE) . . . . . . . . . . . . . .
−0.3
V to V
CC
+ 0.3 V
HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . 25 mA
(Power Dissipation Limited)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65
to 150_C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−40
to 85_C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
Power Dissipation (Package)a
14-Pin Plastic DIP (J Suffix)
b
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW
14-Pin SOIC (Y Suffix)
c
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
Thermal Impedance (Q
JA
)
14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167_C/W
14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 6 mW/_C above 25_C.
c. Derate 7.2 mW/_C above 25_C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltages Referenced to
−V
IN
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 13.5 V
+V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 80 V
f
OSC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz
R
OSC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 1 MW
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
−
3 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
DISCHARGE =
−V
IN
= 0 V
V
CC
= 9 V, +V
IN
= 12 V
R
BIAS
= 270 kW , R
OSC
= 330 kW
OSC IN =
−
V
IN
(OSC Disabled)
R
L
= 10 MW
V
REF
=
−V
IN
Limits
D Suffix
−40
to 85_C
Parameter
Reference
Output Voltage
Output Impedance
e
Short Circuit Current
Temperature Stability
e
Symbol
Temp
b
Room
Full
e
Room
Room
Full
Min
d
3.88
3.82
15
70
Typ
c
4.0
30
100
0.5
Max
e
4.12
4.14
45
130
1.0
Unit
V
R
Z
OUT
I
SREF
T
REF
V
kW
mA
mV/_C
Oscillator
Maximum Frequency
e
Initial Accuracy
Voltage Stability
Temperature Coefficient
e
f
MAX
f
OSC
Df/f
T
OSC
R
OSC
= 0
R
OSC
= 330 k, See Note f
R
OSC
= 150 k, See Note f
Df/f
= f(13.5 V)
−
f(9.5 V) / f(9.5 V)
Room
Room
Room
Room
Full
1
80
160
3
100
200
9
200
120
240
15
500
MHz
kHz
%
ppm/_C
Error Amplifier
Feedback Input Voltage
Input Offset Voltage
Input BIAS Current
Open Loop Voltage Gain
e
Unity Gain Bandwidth
e
Dynamic Output Impedance
e
Output Current
Power Supply Rejection
e
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V
FB
V
OS
I
FB
A
VOL
BW
Z
OUT
I
OUT
PSRR
FB Tied to COMP
OSC IN =
−
V
IN
(OSC Disabled)
OSC IN =
−
V
IN
(OSC Disabled)
OSC IN =
−
V
IN
, V
FB
= 4 V
OSC IN =
−
V
IN
OSC IN =
−
V
IN
(OSC Disabled)
Error Amp Configured for 60 dB gain
Source V
FB
= 3.4 V
Sink V
FB
= 4.5 V
9 V
v
V
CC
v
13.5 V
Room
Room
Room
Room
Room
Room
Room
Room
Room
0.12
50
60
1
3.92
4.00
"15
25
80
1.5
1000
−2.0
0.15
70
2000
−1.4
4.08
"40
500
V
mV
nA
dB
MHz
W
mA
dB
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
2
Si9112
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
DISCHARGE =
−V
IN
= 0 V
V
CC
= 9 V, +V
IN
= 12 V
R
BIAS
= 270 kW , R
OSC
= 330 kW
V
FB
= 0 V
V
SENSE
= 1.5 V, See Figure 1
Limits
D Suffix
−40
to 85_C
Parameter
Current Limit
Threshold Voltage
Delay to Output
e
Symbol
V
SOURCE
t
d
Temp
b
Room
Room
Min
d
1.1
Typ
c
1.3
100
Max
e
1.5
150
Unit
V
ns
Pre-Regulator/Start-Up
Input Voltage
Input Leakage Current
Pre-Regulator Start-Up Current
Pre-Regulator Dropout Voltage
V
CC
Pre-Regulator Turn-Off
Threshold Voltage
Undervoltage Lockout
V
REG
−V
UVLO
+V
IN
+I
IN
I
START
V
CC
V
REG
V
UVLO
V
DELTA
I
IN
= 10
mA
V
CC
w
9.4 V
+V
IN
= 48 V
+V
IN
= 10 V, R
LOAD
= 4 k at Pin 6
I
PRE-REGULATOR
= 10
mA
See Detailed Description
Room
Room
Room
Room
Room
Room
Room
12
V
UVLO
+0.1
8.0
7.2
0.3
8.7
8.1
0.6
9.4
8.9
V
20
80
10
V
mA
mA
Supply
Supply Current
Bias Current
I
CC
I
BIAS
C
L
v
75 pF (Pin 4)
Room
Room
0.6
15
1.0
mA
mA
Logic
SHUTDOWN Delay
e
SHUTDOWN Pulse Width
e
RESET Pulse Width
e
Latching Pulse Width
SHUTDOWN and RESET Low
e
Input Low Voltage
Input High Voltage
Input Current Input Voltage High
Input Current Input Voltage Low
t
SD
t
SW
t
RW
t
LW
V
IL
V
IH
I
IH
I
IL
V
LOGIC
= V
CC
V
IN
= 0 V
See Figure 3
C
L
= 500 pF
V
SENSE
=
−V
IN
, See Figure 2
Room
Room
Room
Room
Room
Room
Room
Room
−35
7.0
1
25
5
mA
50
50
25
2.0
V
50
100
ns
Output
Output High Voltage
Output Low Voltage
Output Resistance
e
Rise Time
e
Fall Time
e
V
OH
V
OL
R
OUT
t
r
t
f
I
OUT
=
−10
mA
I
OUT
= 10 mA
I
OUT
= 10 mA, Source or Sink
C
L
= 500 pF
Room
Full
Room
Full
Room
Full
Room
Room
20
25
40
40
8.7
8.5
0.3
0.5
30
50
75
75
V
W
ns
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f.
C
STRAY
Pin 8 =
v
5 pF.
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
www.vishay.com
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Si9112
Vishay Siliconix
TIMING WAVEFORMS
SENSE
0
V
CC
OUTPUT
0
−
1.5 V
−
50%
t
d
t
r
v
10 ns
V
CC
SHUTDOWN
0
V
CC
OUTPUT
0
50%
−
t
SD
t
f
v
10 ns
90%
90%
−
FIGURE 1.
FIGURE 2.
V
CC
SHUTDOWN
0
V
CC
RESET
0
50%
−
50%
−
t
SW
50%
t
LW
50%
t
RW
50%
t
f
, t
f
v
10 ns
FIGURE 3.
TYPICAL CHARACTERISTICS
+V
IN
vs. +I
IN
at Start-Up
140
V
CC
=
−V
IN
120
100
+V IN (V)
80
60
40
20
0
10
15
+I
IN
(mA)
20
10 k
10 k
f OUT (Hz)
1M
Output Switching Frequency
vs. Oscillator Resistance
100 k
100 k
r
OSC
−
Oscillator Resistance (W)
1M
FIGURE 4.
FIGURE 5.
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Document Number: 70005
S-42036—Rev. H, 15-Nov-04
Si9112
Vishay Siliconix
PIN CONFIGURATIONS AND ORDERING INFORMATION
Dual-In-Line and SOIC
BIAS
+V
IN
SENSE
OUTPUT
−V
IN
V
CC
OSC OUT
1
2
3
4
5
6
7
Top View
14 FB
13 COMP
12 RESET
11 SHUTDOWN
10 V
REF
9
8
DISCHARGE
OSC IN
ORDERING INFORMATION
Part Number
Si9112DY
Si9112DY-T1
Si9112DY-T1—E3
Si9112DJ
Si9112DJ—E3
−40
to 85_C
PDIP-14
SOIC-14
Temperature Range
Package
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section
Due to the low quiescent current requirement of the Si9112
control circuitry, bias power can be supplied from the
unregulated input power source, from an external regulated
low-voltage supply, or from an auxiliary “bootstrap” winding on
the output inductor or transformer.
When power is first applied during start-up, +V
IN
(pin 2) will
draw a constant current. The magnitude of this current is
determined by a high-voltage depletion MOSFET device
which is connected between +V
IN
and V
CC
(pin 6). This
start-up circuitry provides initial power to the IC by charging an
external bypass capacitance connected to the V
CC
pin. The
charging current is disabled when V
CC
exceeds 8.7 V. If V
CC
is
not forced to exceed the 8.7-V threshold, then V
CC
will be
regulated to a nominal value of 8.7 V by the pre-regulator
circuit.
As the supply voltage rises toward the normal operating
conditions, an internal undervoltage (UV) lockout circuit keeps
the output driver disabled until V
CC
exceeds the UV lockout
threshold (typically 8.1 V). This guarantees that the control
logic will be functioning properly and that sufficient gate drive
voltage is available before the MOSFET turns on. The design
of the IC is such that the undervoltage lockout threshold will be
at least 300 mV less than the pre-regulator turn-off voltage.
Power dissipation can be minimized by providing an external
power source to V
CC
such that the pre-regulator circuit is
disabled.
BIAS
To properly set the bias for the Si9112, a 270-k
W
resistor
should be tied from BIAS (pin 1) to
−V
IN
(pin 5). This
Document Number: 70005
S-42036—Rev. H, 15-Nov-04
determines the magnitude of bias current in all of the analog
sections and the pull-up current for the SHUTDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15
mA.
Reference Section
The reference section of the Si9112 consists of a temperature
compensated buried zener and trimmable divider network.
The output of the reference section is connected internally to
the non-inverting input of the error amplifier. Nominal reference
output voltage is 4 V. The trimming procedure that is used on
the Si9112 brings the output of the error amplifier (which is
configured for unity gain during trimming) to within
"2%
of 4 V.
This automatically compensates for input offset voltage in the
error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external voltage
source can be used to override the internal voltage source, if
desired, without otherwise altering the performance of the
device.
Error Amplifier
Closed-loop regulation is provided by the error amplifier. The
emitter follower output has a typical dynamic output
impedance of 1000
W
, and is intended for use with
“around-the-amplifier” compensation. A MOS differential input
stage provides low input leakage current. The noninverting
input to the error amplifier (V
REF
) is internally connected to the
output of the reference supply and should be bypassed with a
small capacitor to ground.
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