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IDT49FCT805APYI

产品描述Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SSOP-20
产品类别逻辑    逻辑   
文件大小74KB,共7页
制造商IDT (Integrated Device Technology)
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IDT49FCT805APYI概述

Low Skew Clock Driver, FCT Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SSOP-20

IDT49FCT805APYI规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码SSOP
包装说明SSOP-20
针数20
Reach Compliance Codenot_compliant
其他特性MONITOR OUTPUT; MAX PART TO PART SKEW = 1.5NS
系列FCT
输入调节SCHMITT TRIGGER
JESD-30 代码R-PDSO-G20
JESD-609代码e0
长度7.2 mm
逻辑集成电路类型LOW SKEW CLOCK DRIVER
最大I(ol)0.064 A
湿度敏感等级1
功能数量2
反相输出次数
端子数量20
实输出次数5
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码SSOP
封装等效代码SSOP20,.3
封装形状RECTANGULAR
封装形式SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度)225
电源5 V
Prop。Delay @ Nom-Sup5.3 ns
传播延迟(tpd)5.3 ns
认证状态Not Qualified
Same Edge Skew-Max(tskwd)0.7 ns
座面最大高度1.99 mm
最大供电电压 (Vsup)5.25 V
最小供电电压 (Vsup)4.75 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度5.3 mm
Base Number Matches1

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IDT49FCT805/A
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805/A
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew < 700ps (max.)
Low duty cycle distortion < 1ns (max.)
Low CMOS power levels
TTL compatible inputs and outputs
Rail-to-rail output voltage swing
High drive: -24mA I
OH
, +64mA I
OL
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
Available in SSOP and SOIC packages
DESCRIPTION:
The 49FCT805 is a non-inverting buffer/clock driver built using ad-
vanced dual metal CMOS technology. Each bank consists of two banks of
drivers. Each bank drives five output buffers from a standard TTL
compatible input. These devices feature a “heart-beat” monitor for
diagnostics and PLL driving. The MON output is identical to all other outputs
and complies with the output specifications in this document.
The 49FCT805 offers low capacitance inputs and hysteresis. Rail-to-rail
output swing improves noise margin and allows easy interface with CMOS
inputs.
NOTE: EOL for non-green parts to occur on 5/13/10 per
PDN U-09-01
FUNCTIONAL BLOCK DIAGRAM
OE
A
IN
A
5
OA
1
-OA
5
IN
B
5
OB
1
-OB
5
OE
B
MON
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
c
2006
Integrated Device Technology, Inc.
SEPT. 2009
DSC-5836/5

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