IR 3/16 Encode/Decode IC
Technical Data
HSDL-7001-2500 pc, tape
and reel
HSDL-7001#100-100pc,
50/tube
Features
• Compliant with IrDA 1.0
Physical Layer Specs
• Interfaces with IrDA 1.0
Compliant IR Transceivers
• Used in Conjunction with
Standard 16550 UART
• Transmits/Receives either
1.63
µ
s or 3/16 Pulse Mode
• Internal or External Clock
Modes
• Programmable Baud Rate
• 2.7-5.5 V Operation
• 16 Pin SOIC Package
Description
The HSDL-7001 modulates and
demodulates electrical pulses
from Hewlett-Packard’s
HSDL-1001 Infrared transceiver
module and other IrDA-compliant
transceivers. The HSDL-7001 can
be used with a microcontroller/
microprocessor that has a serial
communication interface (UART).
Prior to communication, the
processor selects the transmis-
sion baud rate. Serial data is then
transmitted or received at the
prescribed data rate.
The HSDL-7001 consists of two
state machines – the SIR (Serial
InfraRed) Encode and SIR Decode
blocks. It also contains a
sequential block Clock Divide
which synthesizes the required
internal signal.
The HSDL-7001 can be placed
into the Internal Clock Mode or
External Clock Mode. An external
crystal is needed for the Internal
Clock Mode. In applications
where the external 16XCLK
signal is provided, a crystal is not
needed.
There are two data transmission
modes. Data can be transmitted
and received in either a standard
3/16 modulation mode or a
1.63
µs
pulse mode.
Schematic
TXD
SIR
ENCODE
IR_TXD
/NRST
RCD
SIR
DECODE
IR_RCV
INT_CLOCK
A0
A1
A2
16XCLK
CLOCK
DIVIDE
Applications
• Interfaces with IR
Transceivers in:
- Computer Applications:
Notebook Computers
Sub-notebooks
Desktop PCs
PDAs
Printers
Dongle or other RS-232
adapter
- Telecom Applications:
Modems
Fax Machines
Pagers
Phones
- Handheld Data Collection:
Industrial
Medical
Transportation
PULSEMOD
CLK_SEL
Pin Out
16XCLK
TXD
RCV
A0
A1
A2
CLK_SEL
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OSCIN
OSCOUT
POWERDN
PULSEMOD
IR_TXD
IR_RCV
NRST
2
I/O Pinout List
Pin
1
Name
16XCLK
(SIXTNCK)
Type
DIGIN
Function
Positive edge triggered input clock that is set to 16 times the data
transmission baud rate. The encode and decode schemes require this
signal. The signal is usually tied to a UART’s BAUDOUT signal. The
16XCLK may be provided by application circuitry if BAUDOUT is not
available. This signal is required when the internal clock is not used.
Negative edge triggered input signal that is normally tied to the SOUT
signal of the UART (serial data to be transmitted). Data is modulated
and output as IR_TXD.
Output signal normally tied to SIN signal of a UART (received serial
data). RCV is the demodulated output of IR_RVC.
Clock Multiplex Signal
Clock Multiplex Signal
Clock Multiplex Signal
Used to activate either the Internal or External Clock. A high on this
line activates the External clock (16XCLK) and a low activates the
Internal clock. When the External clock is activated, the internal
oscillator is put in POWERDOWN MODE.
Chip Ground
Active low signal used to reset the IrDA-SIR ENCODE & DECODE
state machine. This signal can be tied to POR (Power On Reset) or V
CC
.
Input from SIR optoelectronics. Input signal is a 3/16th or 1.6
µs
pulse
which is demodulated to generate RCV output signal.
This is the modulated TXD signal.
A high level on this input puts the chip into the monoshot transmit
mode. In this mode, when there is a negative transition on the TXD
input, a rising edge on the internal transmit modulation state machine
will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a
3.6864 MHz crystal, this corresponds to 1.63
µs.
This mode cannot be
used in conjunction with the 16XCLK clock. It is meant to be used with
the external crystal clock. By default, this input pin is pulled to GND.
A high on this input puts only the internal oscillator cell (OSCII) in
POWERDOWN MODE. The cell is normally not powered down.
Oscillator Output
Oscillator Input
Power
2
/TXD
DIGIN
3
4
5
6
7
RCV
A0
A1
A2
CLK_SEL
DIGOUT
DIGIN
DIGIN
DIGIN
DIGIN
8
9
10
11
12
GND
/NRST
/IR_RCV
IR_TXD
PULSEMOD
DIGIN
DIGIN
DIGOUT
DIGIN
(with
pulldown)
13
POWERDN
14
15
16
OSCOUT
OSCIN
V
CC
DIGIN
(with
pulldown)
ANAOUT
ANAIN
Note:
There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLKSEL Pin is asserted
high (External clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the POWERDN Pin is asserted
high.
3
Table 1. Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps)
115200
57600
19200
9600
38400
4800
2400
TEST PURPOSE
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Crystal Freq. Division
Divided by 2
Divided by 4
Divided by 12
Divided by 24
Divided by 6
Divided by 48
Divided by 96
No division
Package Dimensions
–A–
16
9
–B–
P
φ
0.25 (0.010) M
8 PL.
BM
16
1
8
NOTES:
1. DIMENSIONS A AND B ARE DATUMS
AND T IS A DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
3. CONTROLLING DIMENSION: MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
MILLIMETERS
MAX.
MIN.
10.00
9.80
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MAX.
MIN.
0.393
0.386
0.157
0.150
0.068
0.054
0.019
0.014
0.049
0.016
0.060 BSC
0.009
0.008
0.009
0.004
7°
0°
0.244
0.229
0.019
0.010
1
G
C
–T–
D
16 PL.
φ
0.25 (0.010) M T B S A S
K
SEATING
PLANE
M
F
R X 45°
J
DIM.
A
B
C
D
F
G
J
K
M
P
R
R
4
Encoding Scheme
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
16XCLK
TXD
IRTXD
7 CS
3 CS
The encoding scheme relies on a
clock being present, which is set
to 16 times the data transmission
baud rate (16XCLX). The encoder
sends a pulse for every space or
“0” that is sent on the TXD line.
On a high to low transition of the
TXD line, the generation of the
pulse is delayed for 7 clock cycles
of the 16XCLK before the pulse is
set high for 3 clock cycles (or
3/16th of a bit time) and then
subsequently pulled low. This
generates a 3/16th bit time pulse
centered around the bit of
information (“0”) that is being
transmitted.
For consecutive spaces, pulses
with a 1 bit time delay are gener-
ated in series. If a logic 1 (mark)
is sent then the encoder does not
generate a pulse.
Decoding Scheme
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
16XCLK
IRRXD
3 CS
RXD
The IrDA-SIR (Serial InfraRed)
decoding modulation method can
be thought of as a pulse stretch-
ing scheme.
Every high to low transition of
the IR_RXD line signifies the
arrival of a pulse. This pulse
needs to be stretched to
accommodate 1 bit time (or 16
16XCLK cycles). Every pulse that
is received is translated into a “0”
or space on the RXD line equal to
1 bit time.
Note 1: The stretched pulse must
be at least 3/4 of a bit time in
duration to be correctly inter-
preted by a UART.
Note 2: It is recommended that
TXD remains high when not
transmitting. This ensures the
LED is off and will not interfere
with signal reception.
5
Monoshot Operation
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CRYSTAL
CLK
INT CLK
(DIVBY2)
TXD
INTERNAL
IRTXD
OUTPUT
IRTXD
(MONOSHOT)
6 CRYSTAL CYCLES
The figure above illustrates the
operation of the monoshot when
the internal clock is set to divide
by 2 mode, i.e., when A2=0,
A1=0, and A0=0. A rising edge
on the internal modulation state
machine (IRTXD OUTPUT), will
cause the output on the IRTXD to
go up for 6 crystal clock cycles.
With a 3.6864 MHz clock, this
corresponds to a pulse of 1.63
µs.
The duration of this pulse is
independent of the code A2,
A1,A0 and is always 6 clock
cycles of the crystal, corre-
sponding to the monoshot
operation.
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