DATASHEET
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
Description
The ICS527-03 is the most flexible way to generate an
output clock from an input clock with zero skew. The
user can easily configure the device to produce nearly
any output clock that is multiplied or divided from the
input clock. The part supports non-integer
multiplications and divisions. Using Phase-Locked
Loop (PLL) techniques, the device accepts an input
clock up to 200 MHz and produces an output clock up
to 160 MHz.
The ICS527-03 aligns rising edges on CLKIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
ICS527-03
Features
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Packaged as 28 pin SSOP, Pb free (150 mil body)
Synchronizes fractional clocks rising edges
CMOS in to PECL out
Pin selectable dividers
Zero input to output skew
User determines the output frequency - no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz to 200 MHz
Output clock frequencies from 2.5 MHz to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
R6:R0
7
CLKIN
Divide
by 2
1
0
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
FBPECL
FBPECL
Divide
by 2
1
0
Feedback
Divider
2
DIV2
7
F6:F0
GND
PDTS
VCO
Output
Divider
2
VDD
VDD
68 ohm
PECL
180 ohm
VDD
68 ohm
PECL
180 ohm
2
S1:S0
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 1
ICS527-03
REV E 051310
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
R5
R6
DIV2
S0
S1
VDD
FBPECL
FBPECL
GND
CLKIN
PDTS
F0
F1
F2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
PECL
PECL
GND
RES
F6
F5
F4
F3
Output Frequency and Output
Divider Table
S1 S0
0
0
1
1
0
1
0
1
Output Divider
2
4
8
1
Output Frequency (MHz)
10 - 80
5 - 40
2.5 - 20
20 -160
28 pin 150 mil body SSOP
Pin Descriptions
Pin
Number
1,2, 24-28
3
4, 5
6, 23
7
8
9, 20
10
11
12-18
19
21
22
Pin
Name
R5, R6,
R0-R4
DIV2
S0, S1
VDD
FPECL
FPECL
GND
CLKIN
PDTS
F0-F6
RES
PECL
PECL
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
BIAS
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal
pull-up.
Connect to +3.3 V.
PECL feedback input.
Complementary PECL feedback input.
Connect to ground
Clock input.
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Resistor connection to VDD for setting level of PECL outputs.
Complementary PECL input clock.
PECL input clock.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 2
ICS527-03
REV E 051310
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS527-03 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. They
must be connected close to the device to minimize lead
inductance.
FDW + 2
-
FB Frequency
= Input Frequency
×
-----------------------
RDW + 2
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Also, the following operating ranges should be
observed:
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
Input Frequency
-
300kHz
<
------------------------------------------
<
20 MHz
RDW + 2
Determining (setting) the ICS527-03
Dividers
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins directly
to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-03 automatically produces
the correct clock when all components are soldered. It
is also possible to connect the inputs to parallel I/O
ports in order to switch frequencies.
The output of the ICS527-03 can be determined by the
following simple equation:
The output divide should be selected depending on
the frequency of CLK1. The table on page 2 gives
the ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3 which
gives the required 5/4 multiplication. If multiple choices
of dividers are available, then the lowest numbers
should be used. In this example, the output divide (OD)
should be selected to be 2. Then R6:R0 is 0000010,
F6:F0 is 0000011 and S1:S0 is 00. Also, this example
assumes CLK1 is connected to FBIN.
If you need assistance determining the optimum divider
settings, please send an e-mail to ics-mk@icst.com
with the desired input clock and the desired output
frequency.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 3
ICS527-03
REV E 051310
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the right.
VDD
R5
R6
DIV2
S0
0.01 F
R4
R3
R2
R1
R0
VDD
PECL
PECL
GND
RES
F6
F5
F4
F3
560
0.01 F
S1
VDD
FBPECL
FBPECL
GND
CLKIN
PDTS
F0
F1
F2
VDD
50 MHz
PECL output resistor network is not shown, but
is identical to PECL
40 MHz
(PECLIN shown)
50 MHz PECL
50 MHz PECL
Note: The series termination resistor is located before
the feedback
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 4
ICS527-03
REV E 051310
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) PECL termination networks should be located as
close to the outputs as possible.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS527-03. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 5
ICS527-03
REV E 051310
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