74HC590
8-bit binary counter with output register; 3-state
Rev. 3 — 24 February 2016
Product data sheet
1. General description
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The
storage register has parallel (Q0 to Q7) outputs. The binary counter features master reset
counter (MRC) and count enable (CE) inputs. The counter and storage register have
separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are
connected together, the counter state is always one count ahead of the register. Internal
circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided
for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of
the second stage. Cascading for larger count chains can be accomplished by connecting
RCO of each stage to the counter clock (CPC) input of the following stage. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of V
CC
.
2. Features and benefits
Counter and register have independent clock inputs
Counter has master reset
Complies with JEDEC standard no. 7A
Multiple package options
Input levels:
For 74HC590: CMOS level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 2000 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Temperature range Name
74HC590D
74HC590PW
74HC590BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO16
TSSOP16
Description
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
Version
SOT403-1
SOT763-1
Type number Package
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 16 terminals; body
2.5
3.5
0.85 mm
Nexperia
74HC590
8-bit binary counter with output register; 3-state
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC590
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 24 February 2016
2 of 20
Nexperia
74HC590
8-bit binary counter with output register; 3-state
Fig 4.
Logic diagram
74HC590
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 24 February 2016
3 of 20
Nexperia
74HC590
8-bit binary counter with output register; 3-state
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
Q0 to Q7
GND
RCO
MRC
CPC
CE
CPR
OE
V
CC
Pin description
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
ripple carry output (active LOW)
master reset counter input (active LOW)
counter clock input (active HIGH)
count enable input (active LOW)
register clock input (active HIGH)
output enable input (active LOW)
supply voltage
74HC590
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 24 February 2016
4 of 20
Nexperia
74HC590
8-bit binary counter with output register; 3-state
6. Functional description
Table 3.
Inputs
OE
H
L
X
X
X
X
X
X
[1]
[2]
Function table
[1] [2]
Description
CPR
X
X
X
X
X
X
MRC
X
X
X
X
L
H
H
H
CE
X
X
X
X
X
L
L
H
CPC
X
X
X
X
X
X
Q outputs disable
Q outputs enable
counter data stored into register
register stage is not changed
counter clear
advance one count
no count
no count
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition.
RCO = Q0’ · Q1’ · Q2’ · Q3’ · Q4’ · Q5’ · Q6’ · Q7’ (Q0’ to Q7’ are internal outputs of the counter).
Fig 7.
Typical timing sequence
74HC590
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 24 February 2016
5 of 20
PCB设计
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