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AS9C25256M2018L-166TI: 产品描述Dual-Port SRAM, 256KX18, 10ns, CMOS, PQFP144, TQFP-144; 产品类别存储存储; 文件大小1MB，共30页; 制造商Integrated Silicon Solution ( ISSI )

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AS9C25256M2018L-166TI概述

Dual-Port SRAM, 256KX18, 10ns, CMOS, PQFP144, TQFP-144

AS9C25256M2018L-166TI规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
零件包装代码	QFP
包装说明	LFQFP,
针数	144
Reach Compliance Code	compli
ECCN代码	3A991.B.2.A
最长访问时间	10 ns
其他特性	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码	S-PQFP-G144
JESD-609代码	e0
长度	20 mm
内存密度	4718592 bi
内存集成电路类型	DUAL-PORT SRAM
内存宽度	18
功能数量	1
端子数量	144
字数	262144 words
字数代码	256000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	256KX18
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压 (Vsup)	2.6 V
最小供电电压 (Vsup)	2.4 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	20 mm
Base Number Matches	1

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September 2004

Preliminary Information

AS9C25512M2018L

AS9C25256M2018L

2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface

Features

• True Dual-Port memory cells that allow simulta-

neous access of the same memory location

• Organisation: 524,288/262,144 × 18

[1]

• Fully Synchronous, independent operation on

both ports

• Selectable Pipeline or Flow-Through output

mode

• Fast clock speeds in Pipeline output mode: 250

MHz operation (9Gbps bandwidth)

• Fast clock to data access: 2.8ns for Pipeline out-

put mode

• Asynchronous output enable control

• Fast OE access times: 2.8ns

• Double Cycle Deselect (DCD) for Pipeline Out-

put Mode

• 19/18

[1]

-bit counter with Increment, Hold and

Repeat features on each port

Note:

1. AS9C25512M2018L/AS9C25256M2018L

•

Dual Chip enables on both ports for easy

depth expansion

Interrupt and Collision Detection Features

2.5 V power supply for the core

LVTTL compatible, selectable 3.3V or

2.5V power supply for I/Os, addresses,

clock and control signals on each port

Snooze modes for each port for standby

operation

15mA typical standby current in power

down mode

Available in 256-pin Ball Grid Array

(BGA), 144-pin Thin Quad Flatpack

(TQFP) and 208-pin fine pitch Ball Grid

Array (fpBGA)

Supports JTAG features compliant with

IEEE 1149.1

Selection guide

Feature

Minimum cycle time

Maximum Pipeline clock frequency

Maximum Pipeline clock access time

Maximum flow-through clock frequency

Maximum flow-through clock access time

Maximum operating current

Maximum snooze mode current

-250

250

2.8

150

6.5

TBD

-200

200

3.4

133

7.5

350

-166

166

3.6

100

300

-133

7.5

133

4.2

260

Units

MHz

9/24/04; v.1.2

Alliance Semiconductor

P. 1 of 30

AS9C25512M2018L

AS9C25256M2018L

General Description

The AS9C25512M2018L/AS9C25256M2018L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory

device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock-

to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.

Each port contains a 19/18 bit linear burst counter on the input address register that can loop through the whole address sequence. After

externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or

the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,

data, and address inputs provide minimal setup and hold times.

The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write

to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the

reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than

one port at the same time is undefined.

The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs

allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,

permits the on-chip circuitry of each port to enter a very low standby power mode.

AS9C25512M2018L/AS9C25256M2018L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is

controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid

Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP)

Address Counter

The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire

memory array. The Address counter features are discussed below:

Load:

Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional

memories.

Increment:

The address counter has the capability to internally increment the address value, potentially covering the entire memory array.

Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known

location has to be loaded before Increment operation.

Hold:

The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.

Repeat:

The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18

bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known

location has to be loaded before Repeat operation (Refer Counter control truth table for details).

9/24/04, v.1.2

Alliance Semiconductor

P. 3 of 30

AS9C25256M2018L-166TI

AS9C25256M2018L-166TI概述

AS9C25256M2018L-166TI规格参数

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