Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64PHC is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
85pin
1pin
94pin
95pin
10pin
11pin
FEATURES
Frequency
-7
-8
-10
100MHz
100MHz
100MHz
CLK Access Time
(Component SDRAM)
6.0ns(CL=3)
6.0ns(CL=3)
8.0ns(CL=3)
Back side
Front side
124pin
125pin
40pin
41pin
Utilizes industry standard 8M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
168pin
84pin
APPLICATION
PC main memory
MIT-DS-0299-0.0
MITSUBISHI
ELECTRIC
( 1 / 55 )
11/ Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64PHC -7,-8, -10
PIN NO.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PIN NAME
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
NC
NC
VSS
NC
NC
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
NC
PIN NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PIN NAME
VSS
CKE0
/S3
DQMB6
DQMB7
NC
VDD
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
SA0
SA1
SA2
VDD
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PIN NAME
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
NC
NC
VSS
NC
NC
VDD
/WE0
DQMB0
DQMB1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10
BA1
VDD
VDD
CK0
PIN NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PIN NAME
VSS
NC
/S2
DQMB2
DQMB3
NC
VDD
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VDD
NC = No Connection
MIT-DS-0299-0.0
MITSUBISHI
ELECTRIC
( 2 / 55 )
11/ Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/S1
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/S2
/S3
10Ω
D0
D4
D2
D6
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D1
D5
D3
D7
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CK0
CK1
CK2
CK3
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
10Ω
3SDRAMs+10pF
3SDRAMs+10pF
2SDRAMs+15pF
2SDRAMs+15pF
D0 - D9
D0 - D9
D0 - D9
D0 - D9
D0 - D9
D0 - D9
CKE1
CKE0
SERIAL PD
SCL
WP
47K
A0 A1 A2
SA0 SA1 SA2
SDA
3.3V
10K
D5-D9
D0-D4
MIT-DS-0299-0.0
MITSUBISHI
ELECTRIC
( 3 / 55 )
11/ Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
-7,-8,-10
-7,-8
-10
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A8
2BANK
x64
0
LVTTL
10ns
6ns
8ns
non-parity
SPD DATA(hex)
80
08
04
0C
09
02
40
00
01
A0
60
80
00
80
10
00
01
8F
04
06
01
01
00
0E
A0
D0
F0
60
70
80
00
00
14
1E
14
14
1E
32
3C
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
self refresh(15.625uS)
x16
N/A
1
1/2/4/8/Full page
4bank
2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
-7
-8
-10
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
10ns
13ns
15ns
6ns
7ns
8ns
N/A
N/A
20ns
30ns
20ns
20ns
30ns
50ns
60ns
24
SDRAM Access form Clock(2nd highest CAS latency)
-7
-8
-10
tAC for CL=2
25
26
27
28
29
30
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
-7,-8
-10
-7,-8,-10
-7,-8
-10
-7,-8
-10
MIT-DS-0299-0.0
MITSUBISHI
ELECTRIC
( 4 / 55 )
11/ Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64PHC -7,-8, -10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
33
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
-7,-8
-10
-7,-8
-10
64MByte
2ns
N/A
1ns
N/A
2ns
N/A
1ns
N/A
option
-7,-8
-10
10
20
00
10
00
20
00
10
00
00
12
01
0E
4E
4B
1CFFFFFFFFFFFFFF
01
02
03
04
4D4831365336345048432D37202020202020
4D4831365336345048432D38202020202020
4D4831365336345048432D31302020202020
34
35
36-61
62
63
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
-7,-8
-10
-7,-8
-10
rev 1.2A
rev 1
Check sum for -7
Check sum for -8
Check sum for -10
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
73-90
Manufactures Part Number
MH16S64PHC-7
MH16S64PHC-8
MH16S64PHC-10
PCB revision
year/week code
serial number
option
-7,-8
-10
91-92
93-94
95-98
99-125
126
127
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
rrrr
yyww
ssssssss
00
64
66
FF
FD
06
00
100MHz
66MHz
CL=2/3,AP,CK0-3
CL=3,AP,CK0-3
CL=2/3
open
-7
-8
-10
128+
Unused storage locations
MIT-DS-0299-0.0
MITSUBISHI
ELECTRIC
( 5 / 55 )
11/ Jan. /1999
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