Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V7245BATJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard 16M
x 4 dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
PIN CONFIGURATION
85pin
94pin
1pin
10pin
11pin
FEATURES
Type name
MH16V7245BATJ-5
MH16V7245BATJ-6
/RAS
/CAS Address /OE
access access access access
time
time
time
time
Cycle
time
Power
dissipation
(typ.W)
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
95pin
50
60
18
20
30
35
18
20
84
104
7.12
5.95
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . 121mW(Max)
Low operation power dissipation
MH16V7245BATJ -5 . . . . . . . . . . . . . . . . . 8.53W(Max)
MH16V7245BATJ -6 . . . . . . . . . . . . . . . . . 7.88W(Max)
All input,output LVTTL compatible
Includes(0.22uF x 20) decoupling capacitors
4096 refresh cycle every 64ms (A0~A11)
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
124pin
BACK SIDE
125pin
40pin
FRONT SIDE
41pin
APPLICATION
Main memory unit for computers , Microcomputer memory
168pin
84pin
PD&ID TABLE
-5
-6
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 1 / 23 )
5/Nov./1998
Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
Pin No.
Pin Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
DQ16
DQ17
Vss
Reserved
Reserved
Vcc
/WE0
/CAS0
Reserved
/RAS0
/OE0
Vss
A0
A2
A4
A6
A8
A10
NC
Vcc
RFU
RFU
Pin No.
Pin Name
Vss
/OE2
/RAS2
/CAS4
Reserved
/WE2
Vcc
Reserved
Reserved
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
Vss
DQ28
DQ29
DQ30
DQ31
Vcc
DQ32
DQ33
DQ34
DQ35
Vss
PD1
PD3
PD5
PD7
ID0
Vcc
Pin No.
Pin Name
Vss
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
Vss
DQ45
DQ46
DQ47
DQ48
DQ49
Vcc
DQ50
DQ51
DQ52
DQ53
Vss
Reserved
Reserved
Vcc
RFU
Reserved
Reserved
Reserved
RFU
Vss
A1
A3
A5
A7
A9
A11
Reserved
Vcc
RFU
B0
Pin No.
Pin Name
Vss
RFU
Reserved
Reserved
Reserved
/PDE
Vcc
Reserved
Reserved
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
Vss
DQ64
DQ65
DQ66
DQ67
Vcc
DQ68
DQ69
DQ70
DQ71
Vss
PD2
PD4
PD6
PD8
ID1
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Reserved: Reserved use
RFU: Reserved for future use
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 2 / 23 )
5/Nov./1998
Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/CAS0
/WE0
/OE0
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS2
/CAS4
/WE2
/OE2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
PIN NAME
/RAS0, /RAS2
/CAS0, /CAS2
/WE0, /WE2
/OE0, /OE2
A0~A11, B0
DQ0~DQ71
Vcc
Vss
/OE
/OE
/W
/CAS
/RAS
DQ1
~DQ4
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
M5M465405B
D1
/OE
/W
/CAS
M5M465405B
D10
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D2
/OE
/W
/CAS
M5M465405B
D11
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D3
/OE
/W
/CAS
M5M465405B
D12
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D4
/OE
/W
/CAS
M5M465405B
D13
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D5
/OE
/W
/CAS
M5M465405B
D14
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D6
/OE
/W
/CAS
M5M465405B
D15
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D7
/OE
/W
/CAS
M5M465405B
D16
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D8
/OE
/W
/CAS
M5M465405B
D17
/OE
/W
/CAS
/RAS
DQ1
~DQ4
/RAS
DQ1
~DQ4
M5M465405B
D9
M5M465405B
D18
A0
B0
A1~A11
MIT-DS-0277-0.0
D1~D9
D10~D18
D1~D18
Vcc
Vss
C
1
.~C
20
..
D1~D18
& INPUT BUFFER
FUNCTION
ROW ADDRESS STROBE INPUT
COLUMN ADDRESS STROBE INPUT
WRITE CONTROL INPUT
OUTPUT ENABLE INPUT
ADDRESS INPUT
DATA I/O
POWER SUPPLY
GROUND
MITSUBISHI
ELECTRIC
( 3 / 23 )
5/Nov./1998
Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
FUNCTION
The MH16V7245BATJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.
Table 1 Input conditions for each mode
/RAS
ACT
Read
ACT
Write (Early write)
ACT
Write (Delayed write)
ACT
Read-modify-write
ACT
Hidden refresh
/CAS before /RAS refresh ACT
NAC
Standby
Operation
/CAS
ACT
ACT
ACT
ACT
ACT
ACT
DNC
Inputs
/W
/OE
NAC
ACT
ACT
DNC
ACT
DNC
ACT
ACT
DNC
ACT
NAC
DNC
DNC
DNC
Input/Output
Row
Column
address address
APD
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
DNC
Input
OPN
VLD
VLD
VLD
OPN
DNC
DNC
Output
VLD
OPN
IVD
VLD
VLD
OPN
OPN
Refresh
NO
NO
NO
NO
YES
YES
NO
Remark
Hyper page
mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 4 / 23 )
5/Nov./1998
Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
VO
IO
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ratings
-0.5~4.6
-0.5~ 4.6
-0.5~ 4.6
50
21.6
0~70
-40~100
Unit
V
mA
W
°C
°C
Ta=25°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
Min
3.0
0
2.0
-0.3
(Ta=0~70°C, unless otherwise noted) (Note 1)
Limits
Nom
3.3
0
Max
3.6
0
Vcc+0.3
0.8
Unit
V
V
V
V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
II
I I (RAS)
Parameter
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions
IOH=-2mA
IOL=2mA
Q floating 0V≤VOUT≤Vcc
0V≤VIN≤Vcc+0.3, Other input pins=0V
0V≤VIN≤Vcc+0.3, Other input pins=0V
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /RAS)
Input current (/RAS)
Average supply
ICC1 (AV) current
from Vcc operating (Note 3,4,5)
ICC2
Supply current from Vcc , stand-by
Min
2.4
0
-10
-10
-90
Limits
Typ Max
Vcc
0.4
10
10
90
2360
2180
38
29
1820
1640
2360
2180
Unit
V
V
uA
uA
uA
mA
-5
-6
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS=/WE
≥Vcc
-0.2, output open
mA
mA
Average supply current
ICC4(AV) from Vcc
Hyper-Page-Mode (Note 3,4,5)
Average supply current from Vcc
ICC6(AV) /CAS before /RAS refresh mode
(Note 3)
-5
-6
-5
-6
/RAS=VIL,/CAS cycling
tPC=min.
output open
/CAS before /RAS refresh cycling
tRC=min.
output open
mA
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH
CAPACITANCE
Symbol
(Ta = 0~70°C, Vcc = 3.3V+/-0.3V, Vss = 0V, unless otherwise noted)
Parameter
Test conditions
VI=Vss
f=1MHZ
Vi=25mVrms
Min
CI (/RAS) Input capacitance, /RAS input
CI
Input capacitance, except /RAS input
C(DQ)
Input/Output capacitance,DATA
Limits
Typ Max
80
15
18
Unit
pF
pF
pF
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 5 / 23 )
5/Nov./1998
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