Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH1S72CPG is 1048576-word by 64-bit
Synchronous DRAM module. This consists of five
industry standard 1Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
85pin
1pin
FEATURES
Frequency
-10
-12
-15
100MHz
83MHz
67MHz
CLK Access Time
(Component SDRAM)
94pin
95pin
10pin
11pin
8ns(CL=3)
8ns (CL=3)
Back side
9ns (CL=3)
Front side
Utilizes industry standard 1M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
124pin
125pin
40pin
41pin
single 3.3V±0.3V power supply
Clock frequency 100MHz/83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
168pin
84pin
APPLICATION
main memory or graphic memory in computer systems
Module item "-10","-12" , and "-15" show mounted SDRAM devices Cycle time(min.).
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 1 / 47 )
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
PIN CONFIGURATION
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PIN NAME
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
/WE
DQMB0
DQMB1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10
NC
VDD
VDD
CK0
PIN NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PIN NAME
VSS
NC
/S2
DQMB2
DQMB3
NC
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
NC
SDA
SCL
VDD
PIN NO.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PIN NAME
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
/CAS
DQMB4
DQMB5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA
NC
VDD
CK1
NC
PIN NO.
127
128
129
130
131
132
133
134
135
CB6
CB7
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PIN NAME
VSS
CKE0
NC
DQMB6
DQMB7
NC
VDD
NC
NC
NC
NC
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
SA0
SA1
SA2
VDD
NC = No Connection
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 2 / 47 )
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
Block Diagram
CKE
/WE
/CAS
/RAS
/S2
/S0
CK0
CLK CS RAS CAS WE CKE
CLK CS RAS CAS WE CKE
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQML
DQ0~DQ7
DQMU
D0
DQ8~DQ15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML
I/O0
I/O1
I/O2
DQ0~DQ7
I/O3
D4
I/O4
I/O5
I/O6
I/O7
DQMU
D2
DQ8~DQ15
CLK CS RAS CAS WE CKE
CLK CS RAS CAS WE CKE
DQML
DQML
DQ0~DQ7
D2
DQ0~DQ7
DQMU
D1
DQMU
D3
DQ8~DQ15
DQ8~DQ15
CLK CS RAS CAS WE CKE
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQML
DQMU
D4
CK1
CK2
CK3
BA,A(10:0)
Vcc
Resister
CK,DQ,CB = 10Ω
others = 0Ω
D0 to D4
D0 to D4
D0 to D4
SCL
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
Vss
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 3 / 47 )
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte
0
1
2
3
4
5
6
7
8
9
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
Cycle time for CL=1
26
SDRAM Access form Clock(3rd highest CAS latency)
tAC for CL=1
27
Precharge to Active Minimum
-10
-12
-15
-10
-12
-15
-10
-12
-15
-10
-12
-15
-10
-12
-15
28
Row Active to Row Active Min.
-10
-12
-15
-10
-12
-15
-10
-12
-15
SPD enrty data
128
256 Bytes
SDRAM
A0-A10
A0-A7
1BANK
x72
0
LVTTL
10ns
12ns
15ns
8ns
8ns
9ns
ECC
SPD DATA(hex)
80
08
04
0B
08
01
48
00
01
A0
C0
F0
80
80
90
02
80
10
08
01
0F
02
06
01
01
00
06
F0
F0
FF
90
95
C0
78
78
78
6C
6C
78
1E
1E
28
14
18
1E
self refresh(15.625uS)
x16
x8
1
1/2/4/8
2bank
CL=1/2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
15ns
15ns
20ns
9ns
9.5ns
12ns
30ns
30ns
30ns
27ns
27ns
30ns
30ns
30ns
40ns
20ns
24ns
30ns
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 4 / 47 )
28.Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH1S72CPG-10,-12,-15
75497472-BIT (1048576-WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table
29
RAS to CAS Delay Min
-10
-12
-15
30
Active to Precharge Min
-10
-12
-15
31
32-61
62
63
Density of each bank on module
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
30ns
30ns
30ns
60ns
70ns
80ns
8MByte
option
rev 1
Check sum for -10
Check sum for -12
Check sum for -15
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
73-90
Manufactures Part Number
MH1S72CPG-10
MH1S72CPG-12
MH1S72CPG-15
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
PCB revision
year/week code
serial number
option
66MHz
CL=3: 04H, CL=2/3: 06H
open
1E
1E
1E
3C
46
50
02
00
01
B6
E9
89
1CFFFFFFFFFFFFFF
01
02
03
04
4D48315337324350472D3130202020202020
4D48315337324350472D3132202020202020
4D48315337324350472D3135202020202020
rrrr
yyww
ssssssss
00
66
06
00
MIT-DS-0089-3.0
MITSUBISHI
ELECTRIC
( 5 / 47 )
28.Mar.1997
实时操作系统RTOS
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