Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
DESCRIPTION
The MH4V36AM is an 4M word by 36-bit dynamic
RAM module and consists of 2 industry standard
4M X 16 dynamic RAMs in TSOP and 1 industry
standard 4M X 4(4CAS) dynamic RAMs in TSOP.
The ICs are mounted on both sides of one small
ceracom PC board with flash gold plating and form a
convenient 68-pin package.
PIN CONFIGURATION ( TOP VIEW )
FEATURES
Type name
Address
OE
RAS
CAS
Cycle
access access access
access
time
time
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
MH4V36AM-6
MH4V36AM-7
60
70
15
20
30
35
15
20
110
130
Utilizes industry standard 4M X 16 DRAMs in TSOP package
and industry standard 4M X 4(4CAS) DRAM in TSOP
package
Single 3.3V +/- 0.3V supply
Low stand-by power dissipation
5.4mW (Max) . . . . . . . . . . . . . . . . . CMOS lnput level
Low operating power dissipation
MH4V36AM - 6 . . . . . . . . . . . . . . . . 1.155W (Max)
MH4V36AM - 7 . . . . . . . . . . . . . . . . 1.100W (Max)
All inputs, output TTL compatible and low capacitance
4096 refresh cycles every 64ms (A
0
~ A
11
)
Includes 2pcs 0.22uF decoupling capacitors
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
DQ1 1
DQ2 2
DQ3 3
DQ4 4
DQ5 5
Vss 6
DQ6 7
DQ7 8
DQ8 9
DQP1 10
DQ9 11
Vcc 12
DQ10 13
DQ11 14
DQ12 15
DQ13 16
DQ14 17
Vss 18
DQ15 19
DQ16 20
DQP2 21
Vcc 22
/CAS0 23
/CAS3 24
A0 25
A1 26
A2 27
Vss 28
A3 29
A4 30
A5 31
/RAS 32
A6 33
Vcc 34
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
DQP4
DQ32
DQ31
DQ30
DQ29
Vss
DQ28
DQ27
DQ26
DQ25
DQP3
Vcc
DQ24
DQ23
DQ22
DQ21
DQ20
Vss
DQ19
DQ18
DQ17
Vcc
/CAS2
/CAS1
/W
/OE
RFU(NC)
Vss
A11
A10
A9
A8
A7
Vcc
MIT-DS-0071-0.1
MITSUBISHI
ELECTRIC
( 1 / 18 )
Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
FUNCTION
The MH4V36AM provide, in addition to normal read,
write, and read-modify-write operations, a number of
other functions, e.g., fast page mode, CAS before RAS refresh,
and delayed-write. The input conditionsfor each are shown in
Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
RAS
Read
Write
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
NAC
ACT
ACT
DNC
W
NAC
ACT
ACT
DNC
DNC
NAC
DNC
OE
ACT
NAC
ACT
DNC
ACT
DNC
DNC
Input
OPN
VLD
VLD
DNC
OPN
DNC
DNC
Output
VLD
OPN
VLD
OPN
VLD
OPN
OPN
Input/Output
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open
BLOCK DIAGRAM
Add
/W
/OE
/CAS3
/CAS2
/CAS1
/CAS0
/RAS
25,26,27,29,30,31,33,36,37,38,39,40
44
43
24
46
45
23
32
/RAS /UCAS
/LCAS
/OE
/W Add
/RAS
/UCAS
/LCAS
/OE
/W Add
/RAS /CAS1
/CAS3
/OE
/CAS2
/CAS4
DQ2 DQ3 DQ4
/W
Add
M5M465160A
M5M465160A
M5M4V17500B
DQ1
68
58
21
10
DQP4
DQP3
DQP2
DQP1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
11
13
14
15
16
17
19
20
48
49
50
52
53
54
55
56
12 22 34 35 47 57
01
02
03
04
05
07
08
09
C1 to C2
0.22 uF
59
60
61
62
64
65
66
67
6
18 28 41 51 63
Vcc
Vss
MIT-DS-0071-0.1
MITSUBISHI
ELECTRIC
( 2 / 18 )
Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
V0
I0
Pd
Topr
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
3
0 ~ 70
-40 ~ 100
Unit
V
V
V
mA
W
°C
°C
Ta=25°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
(Ta=0 ~70 °C
, unless otherwise noted)
(Note 1)
Min
3.0
0
3.0
-0.3
Limits
Nom
3.3
0
Max
3.6
0
3.6
0.8
Unit
V
V
V
V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
II
Parameter
(Ta=0 ~70 °C, Vcc=3.3V+/- 0.3V, Vss=0V, unless otherwise noted)
(Note 2)
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V
≤
VOUT
≤
3.6V
0V
≤
VIN
≤
3.6V, Other inputs pins = 0V
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply
current
ICC1 (AV)
from Vcc operating
(Note 3,4,5)
ICC2
Min
2.4
0
-10
-30
Limits
Typ Max
Vcc
0.4
10
30
380
Unit
V
V
µA
µA
mA
-6
-7
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
RAS= CAS≥Vcc -0.2V, output open
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min. , W
≥
Vcc - 0.2
output open
305
4
1.4
260
mA
240
380
mA
365
mA
Supply current from Vcc , stand-by
Average supply current
from Vcc
Fast-Page-Mode
(Note 3,4,5)
Average supply current
from Vcc
CAS before RAS refresh
(Note 3,5)
mode
-6
-7
-6
-7
ICC4(AV)
ICC6(AV)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be channged once or less while RAS=VIL and CAS=VIH
CAPACITANCE
Symbol
CI (A)
(Ta=0~70°C , Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted)
Parameter
Test conditions
Min
Limits
Typ
Max
30
Unit
pF
pF
pF
pF
pF
pF
Input capacitance,
address inputs
CI (OE) Input capacitance, OE input
CI (W)
Input capacitance, write control input
CI (RAS) Input capacitance, RAS input
CI (CAS) Input capacitance, CAS input
CI / O
Input/Output capacitance, data ports
MIT-DS-0071-0.1
VI=Vss
f=1MHZ
Vi=25mVrms
36
36
36
30
25
MITSUBISHI
ELECTRIC
( 3 / 18 )
Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
CLZ
t
OFF
t
OEZ
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output disable time after CAS high
Output disable time after OE high
(Ta=0~70°C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
Limits
Parameter
Min
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
5
0
0
15
15
(Note 12)
(Note 12)
-6
Max
15
60
30
35
15
5
0
0
15
15
Min
-7
Max
20
70
35
40
20
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Output low impedance time from CAS low (Note 7)
Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-Only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that t
RCD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max).
9: Assumes that t
RCD
≤
t
RCD(max)
and t
RAD
≤
t
RAD(max).
If t
RCD
or t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that t
RCD
exceeds the value shown.
10: Assumes that t
RAD
≥
t
RAD(max)
and t
ASC
≤
t
ASC(max).
11: Assumes that t
CP
≤
t
CP(max)
and t
ASC
≥
t
ASC(max).
12: t
OFF(max)
and t
OEZ (max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
I +/- 10 µAI) and is not reference to
V
OH(min)
or V
OL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 °C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 13,14)
Limits
Symbol
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
CDD
t
ODD
t
T
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Parameter
Min
40
(Note15)
20
10
0
10
(Note16)
(Note17)
15
0
0
10
15
0
0
15
15
1
-6
Max
64
50
45
20
10
0
10
30
10
15
0
0
10
15
0
0
15
15
50
1
Min
-7
Max
64
50
Unit
ms
ns
ns
ns
ns
ns
35
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
(Note18)
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
Delay time, OE high to data
Transition time
(Note18)
(Note19)
(Note19)
(Note20)
Note 13: The timing requirements are assumed t
T
=5ns.
14: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
15: t
RCD(max)
is specified as a reference point only. If t
RCD
is less than t
RCD(max),
access time is t
RAC.
If t
RCD
is greater than t
RCD(max),
access
time is controlled exclusively by t
CAC
or t
AA.
t
RCD(min)
is specified as t
RCD(min)
=t
RAH(min)
+2t
H
+t
ASC(min).
16: t
RAD(max)
is specified as a reference point only. If t
RAD≥
t
RAD(max)
and t
ASC
≤
t
ASC(max),
access time is controlled exclusively by t
AA.
17: t
ASC(max)
is specified as a reference point only. If t
RCD≥
t
RCD(max)
and t
ASC
≥
t
ASC(max),
access time is controlled exclusively by t
CAC.
18: Either t
DZC
or t
DZO
must be satisfied.
19: Either t
CDD
or t
ODD
must be satisfied.
20: t
T
is measured between V
IH(min)
and V
IL(max).
MIT-DS-0071-0.1
MITSUBISHI
ELECTRIC
( 4 / 18 )
Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
OCH
t
ORH
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time after CAS high
Read hold time after CAS low
Read hold time after RAS low
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low
(Note 21)
(Note 21)
Parameter
Min
110
60
15
60
15
0
0
10
30
15
15
10000
10000
-6
Max
Min
130
70
20
70
20
0
0
10
35
20
20
10000
10000
-7
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Note 21: Either t
RCH
or t
RRH
must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
t
WC
t
RAS
t
CAS
t
CSH
t
RSH
t
WCS
t
WCH
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
OEH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
(Note 23)
Parameter
Min
110
60
15
60
15
0
10
15
15
10
0
10
15
10000
10000
-6
Max
Min
130
70
20
70
20
0
10
20
20
10
0
15
20
10000
10000
-7
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MIT-DS-0071-0.1
MITSUBISHI
ELECTRIC
( 5 / 18 )
Sep./19 /1996
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