Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64S64APFH-6,-6L,-7,-7L

4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

DESCRIPTION

The MH64S64APFH is 67108864 - word by 64-bit

Synchronous DRAM module. This consists of

sixteen industry standard 32Mx8 Synchronous

DRAMs in Small TSOP and one industory

standard EEPROM in TSSOP.

The mounting of Small TSOP on a card edge

Dual Inline package provides any application

where high densities and large quantities of

memory are required.

This is a socket type - memory modules, suitable

for easy interchange or addition of modules.

Utilizes industry standard 32M x 8 Sy nchronous DRAMs

Small TSOP and industry standard EEPROM in TSSOP

144-pin (72-pin dual in-line package)

single 3.3V±0.3V power supply

Max. Clock frequency -6:133MHz,-7:100MHz

Fully synchronous operation referenced to clock rising

edge

4 bank operation controlled by BA0,1(Bank Address)

/CAS latency- 2/3(programmable)

Burst length- 1/2/4/8/Full Page(programmable)

FEATURES

Frequency

-6,-6L

-7,-7L

133MHz

100MHz

CLK Access Time

(Component SDRAM)

Burst type- sequential / interleave(programmable)

Column access - random

Auto precharge / All bank precharge controlled by A10

Auto refresh and Self refresh

8192 refresh cycle /64ms

LVTTL Interface

5.4ns(CL=3)

6.0ns(CL=2)

APPLICATION

main memory or graphic memory in computer systems

PCB Outline

(Front)

(Back)

1

2

143

144

MIT-DS-0392-0.1

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ELECTRIC

( 1 / 52 )

16.Apr.2000

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64S64APFH-6,-6L,-7,-7L

4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

PIN CONFIGURATION

Number

Front side

Pin Name

Number

Back side

Pin Name

Number

Front side

Pin Name

Number

Back side

Pin Name

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

Vss

DQ0

DQ1

DQ2

DQ3

Vcc

DQ4

DQ5

DQ6

DQ7

Vss

DQMB0

DQMB1

Vcc

A0

A1

A2

Vss

DQ8

DQ9

DQ10

DQ11

Vcc

DQ12

DQ13

DQ14

DQ15

Vss

NC

CLK0

Vcc

/RAS

/WE

/S0

/S1

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

Vss

DQ32

DQ33

DQ34

DQ35

Vcc

DQ36

DQ37

DQ38

DQ39

Vss

DQMB4

DQMB5

Vcc

A3

A4

A5

Vss

DQ40

DQ41

DQ42

DQ43

Vcc

DQ44

DQ45

DQ46

DQ47

Vss

NC

CKE0

Vcc

/CAS

CKE1

A12

NC

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

NC

Vss

NC

Vcc

DQ16

DQ17

DQ18

DQ19

Vss

DQ20

DQ21

DQ22

DQ23

Vcc

A6

A8

Vss

A9

A10

Vcc

DQMB2

DQMB3

Vss

DQ24

DQ25

DQ26

DQ27

Vcc

DQ28

DQ29

DQ30

DQ31

Vss

SDA

Vcc

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

CLK1

Vss

NC

Vcc

DQ48

DQ49

DQ50

DQ51

Vss

DQ52

DQ53

DQ54

DQ55

Vcc

A7

BA0

Vss

BA1

A11

Vcc

DQMB6

DQMB7

Vss

DQ56

DQ57

DQ58

DQ59

Vcc

DQ60

DQ61

DQ62

DQ63

Vss

SCL

Vcc

NC = No Connection

MIT-DS-0392-0.1

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ELECTRIC

( 2 / 52 )

16.Apr.2000

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64S64APFH-6,-6L,-7,-7L

4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

Block Diagram

/S0

/S1

DQMB0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQM /CS

DQMB4

I/O

0

1

2

3

4

5

6

7

I/O

0

1

2

3

4

5

6

7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB5

I/O

0

1

2

3

4

5

6

7

I/O

0

1

2

3

4

5

6

7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQMB6

I/O

0

1

2

3

4

5

6

7

DQM /CS

D0

D8

I/O

0

1

2

3

4

5

6

7

D4

I/O

0

1

2

3

4

5

6

7

D12

D1

D9

I/O

0

1

2

3

4

5

6

7

D5

I/O

0

1

2

3

4

5

6

7

D13

D2

I/O

0

1

2

3

4

5

6

7

D10

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB7

DQM /CS

I/O

0

1

2

3

4

5

6

7

D6

I/O

0

1

2

3

4

5

6

7

D14

I/O

0

1

2

3

4

5

6

7

DQM /CS

D3

I/O

0

1

2

3

4

5

6

7

D11

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM /CS

I/O

0

1

2

3

4

5

6

7

D7

I/O

0

1

2

3

4

5

6

7

D15

/RAS

/CAS

/WE

BA0,BA1,A<12:0>

Vcc

CK,DQ=10Ω

D0

-

D15 CKE0

D15

D15 CKE1

D15

D0 - D7 CK0

CK1

D8 - D15

SCL

8SDRAMs

SERIAL PD

A0

A1

A2

SDA

Vss

D0 - D15

MIT-DS-0392-0.1

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ELECTRIC

( 3 / 52 )

16.Apr.2000

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64S64APFH-6,-6L,-7,-7L

4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

Serial Presence Detect Table I

Byte

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Function described

Defines # bytes written into serial memory at module mfgr

Total # bytes of SPD memory device

Fundamental memory type

# Row Addresses on this assembly

# Column Addresses on this assembly

# Module Banks on this assembly

Data Width of this assembly...

... Data Width continuation

Voltage interface standard of this assembly

SDRAM Cycletime at Max. Supported CAS Latency (CL).

-6,-6L

-7,-7L

-6,-6L

-7,-7L

SPD enrty data

128

256 Bytes

SDRAM

A0-A12

A0-A9

2BANK

x64

0

LVTTL

7.5ns

10ns

5.4ns

6ns

Non-PARITY

SPD DATA(hex)

80

08

04

0D

0A

02

40

00

01

75

A0

54

60

00

82

08

00

01

8F

04

06

01

00

0E

A0

Cycle time for CL=3

SDRAM Access from Clock

tAC for CL=3

DIMM Configuration type (Non-parity,Parity,ECC)

Refresh Rate/Type

SDRAM width,Primary DRAM

Error Checking SDRAM data width

self refresh(7.8uS)

x8

N/A

1

1/2/4/8/Full page

4bank

2/3

0

non-buffered,non-registered

Precharge All,Auto precharge

Minimum Clock Delay,Back to Back Random Column Addresses

Burst Lengths Supported

# Banks on Each SDRAM device

CAS# Latency

CS# Latency

Write Latency

SDRAM Module Attributes

SDRAM Device Attributes:General

SDRAM Cycle time(2nd highest CAS latency)

Cycle time for CL=2

SDRAM Access form Clock(2nd highest CAS latency)

10ns

24

tAC for CL=2

25

26

27

28

29

SDRAM Cycle time(3rd highest CAS latency)

SDRAM Access form Clock(3rd highest CAS latency)

6ns

60

N/A

20ns

-6,-6L

-7,-7L

00

14

0F

14

2D

32

Precharge to Active Minimum

Row Active to Row Active Min.

RAS to CAS Delay Min

Active to Precharge Min

15ns

20ns

45ns

50ns

-7,-7L

-6,-6L

-7,-7L

30

MIT-DS-0392-0.1

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ELECTRIC

( 4 / 52 )

16.Apr.2000

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64S64APFH-6,-6L,-7,-7L

4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

Serial Presence Detect Table II

31

32

33

34

Density of each bank on module

Command and Address signal input setup time

Command and Address signal input hold time

-6,-6L

-7,-7L

-6,-6L

-7,-7L

256MByte

1.5ns

2ns

0.8ns

1ns

1.5ns

2ns

0.8ns

1ns

option

rev 1.2B

Check sum for -6,-6L

40

15

20

08

10

15

20

08

10

00

12

D3

3A

1CFFFFFFFFFFFFFF

01

02

03

04

4D483634533634415046482D362020202020

4D483634533634415046482D364C20202020

4D483634533634415046482D372020202020

4D483634533634415046482D374C20202020

Data signal input setup time

-6,-6L

-7,-7L

35

36-61

62

Data signal input hold time

Superset Information (may be used in future)

SPD Revision

-6,-6L

-7,-7L

63

64-71

Checksum for bytes 0-62

Check sum for -7,-7L

Manufactures Jedec ID code per JEP-108E

MITSUBISHI

Miyoshi,Japan

Tajima,Japan

NC,USA

Germany

MH64S64APFH-6

MH64S64APFH-6L

72

Manufacturing location

73-90

Manufactures Part Number

MH64S64APFH-7

MH64S64APFH-7L

91-92

93-94

95-98

99-125

126

Revision Code

Manufacturing date

Assembly Serial Number

Manufacture Specific Data

Intetl specification frequency

PCB revision

year/week code

serial number

option

100MHz

rrrr

yyww

ssssssss

00

64

127

128+

Intel specification CAS# Latency support

Unused storage locations

CL=2/3,AP,CK0,1

open

CF

00

MIT-DS-0392-0.1

MITSUBISHI

ELECTRIC

( 5 / 52 )

16.Apr.2000

参数名称	属性值
厂商名称	Mitsubishi(日本三菱)
零件包装代码	DIMM
包装说明	DIMM, DIMM144,32
针数	144
Reach Compliance Code	unknow
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	5.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N144
内存密度	4294967296 bi
内存集成电路类型	SYNCHRONOUS DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	144
字数	67108864 words
字数代码	64000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64MX64
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM144,32
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
电源	3.3 V
认证状态	Not Qualified
刷新周期	8192
自我刷新	YES
最大待机电流	0.016 A
最大压摆率	2.88 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	3.3 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	0.8 mm
端子位置	DUAL

	MH64S64APFH-6	MH64S64APFH-7L	MH64S64APFH-7	MH64S64APFH-6L
描述	4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM	4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM	4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM	4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM
零件包装代码	DIMM	DIMM	DIMM	DIMM
包装说明	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32
针数	144	144	144	144
Reach Compliance Code	unknow	unknow	unknow	unknow
ECCN代码	EAR99	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	5.4 ns	6 ns	6 ns	5.4 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	100 MHz	100 MHz	133 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-XDMA-N144	R-XDMA-N144	R-XDMA-N144	R-XDMA-N144
内存密度	4294967296 bi	4294967296 bi	4294967296 bi	4294967296 bi
内存集成电路类型	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
内存宽度	64	64	64	64
功能数量	1	1	1	1
端口数量	1	1	1	1
端子数量	144	144	144	144
字数	67108864 words	67108864 words	67108864 words	67108864 words
字数代码	64000000	64000000	64000000	64000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C
组织	64MX64	64MX64	64MX64	64MX64
输出特性	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM	DIMM
封装等效代码	DIMM144,32	DIMM144,32	DIMM144,32	DIMM144,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
电源	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192
自我刷新	YES	YES	YES	YES
最大待机电流	0.016 A	0.016 A	0.016 A	0.016 A
最大压摆率	2.88 mA	2.72 mA	2.72 mA	2.88 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL	DUAL
厂商名称	Mitsubishi(日本三菱)	Mitsubishi(日本三菱)	Mitsubishi(日本三菱)	-

MH64S64APFH-6

MH64S64APFH-6概述

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