MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change w ithout notice.
DESCRIPTION
The MH64S72QJA is 67108864 - word x 72-bit
Sy nchronous DRAM stacked structural module. This
consist of thirty -six industry s t andard 32M x 4
Sy nchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual in-
line package prov ides any application where high
densities and large of quantities memory are required.
This is a socket-ty pe memory m odule ,suitable f or
easy interchange or addition of module.
85pin
1pin
FEATURES
Type name
Max.
Frequency
CLK
Access Time
[latch mode]
(CL = 4)
CLK
Access Time
[buffer mode]
(CL = 3)
94pin
95pin
10pin
11pin
MH64S72QJA-7
MH64S72QJA-8
100MHz
100MHz
6ns
6ns
6ns
6ns
Utilizes industry standard 32M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V power supply
LVTTL Interface
4096 refresh cycles every 64ms
124pin
125pin
40pin
41pin
APPLICATION
Main memory unit for computers, Microcomputer memory.
168pin
84pin
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
1
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PIN NAME
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
/WE
DQMB0
DQMB1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10
BA1
VDD
VDD
CK0
PIN NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PIN NAME
VSS
NC
/S2
DQMB2
DQMB3
NC
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VDD
PIN NO.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PIN NAME
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
NC
PIN NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PIN NAME
VSS
CKE0
/S3
DQMB6
DQMB7
NC
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
SA0
SA1
SA2
VDD
NC = No Connection
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
2
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add
CKE0
/S0-3
DQM0-7
/W
/RAS
/CAS
REGE
Vdd
RCKE0
R/S0-3
RDQM0-7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CB0
CB1
CB2
CB3
D8
D26
D6
D24
D5
D23
D4
D22
D3
D21
D0
D18
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB4
CB5
CB6
CB7
D17
D35
D15
D33
D14
D32
D13
D31
D12
D30
D9
D27
D1
D19
D10
D28
D2
D20
D11
D29
D7
D25
D16
D34
From PLL
CK0
CK1 - CK3
RCKE0
R/S0
R/S1
R/S2
R/S3
PLL
SERIAL PD
RDQM
RDQM
D0-35
RDQM
D9-12,D17-21,D26
D0-3,D8,D27-30,D35 RDQM
D13-16,D22-25
RDQM
D4-7,D31-34
RDQM
RDQM
RDQM
Terminated
0
1
2
3
4
5
6
7
D0-1,D18-19
WP
D2-3,D8,D20-21,D26
D4-5,D22-23
D6-7,D24-25
D9-10,D27-28
D11-12,D17,D29-30,D35 VDD
D13-14,D31-32
VSS
D15-16,D33-34
SCL
SDA
A0
A1
A2
SA0 SA1 SA2
D0 to D35
D0 to D35
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
3
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A10
2BANK
x72
0
LVTTL
10ns
SPD DATA(hex)
80
08
04
0C
0B
02
48
00
01
A0
60
02
80
04
04
01
8F
04
06
01
01
1F
0E
A0
D0
60
70
00
00
14
14
14
32
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
ECC
6ns
self refresh(15.625uS)
x4
x4
1
1/2/4/8/Full page
4bank
2/3
0
0
buffered,registered
Precharge All,Auto precharge
Write1/Read Burst
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
-7
-8
-7
-8
10ns
13ns
6ns
7ns
N/A
N/A
20ns
20ns
20ns
50ns
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
26
27
28
29
30
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
4
MITSUBISHI LSIs
MH64S72QJA -7,-8
4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31
32
33
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
256MByte
2ns
1ns
40
20
10
20
34
35
36-61
62
63
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
2ns
1ns
option
rev 1.2A
Check sum for -7
Check sum for -8
10
00
12
61
A1
1CFFFFFFFFFFFFFF
01
02
03
04
4D483634533732514A412D37202020202020
4D483634533732514A412D38202020202020
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
73-90
Manufactures Part Number
MH64S72QJA-7
MH64S72QJA-8
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0
open
rrrr
yyww
ssssssss
00
64
8F
00
MIT-DS-0332-0.0
MITSUBISHI
ELECTRIC
16/Jun./1999
5