Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776 -BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
DESCRIPTION
The MH8S72DALD is 8388608 - word by 72-bit
Synchronous DRAM module. This consists of nine
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
85pin
1pin
94pin
95pin
10pin
11pin
FEATURES
Frequency
-6
-7
-8
133MHz
100MHz
100MHz
CLK Access Time
(Component SDRAM)
5.4ns(CL=3)
6.0ns(CL=2)
6.0ns(CL=3)
124pin
125pin
40pin
41pin
Utilizes industry standard 8M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
168pin
84pin
APPLICATION
PC main memory
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 1 / 55 )
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776 -BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PIN NAME
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
/WE0
DQMB0
DQMB1
/S0
NC
VSS
A0
A2
A4
A6
A8
A10
BA1
VDD
VDD
CK0
PIN NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PIN NAME
VSS
NC
/S2
DQMB2
DQMB3
NC
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VDD
PIN NO.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PIN NAME
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
/CAS
DQMB4
DQMB5
NC
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
NC
PIN NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PIN NAME
VSS
CKE0
NC
DQMB6
DQMB7
NC
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
SA0
SA1
SA2
VDD
NC = No Connection
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 2 / 55 )
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776 -BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
Block Diagram
/S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
/S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
DQM /CS
DQM /CS
DQM /CS
DQM /CS
DQMB4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQM /CS
D0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
D4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
0
1
2
3
4
5
6
7
D1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CK0
CK2
CK1
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQM /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5SDRAMs
4SDRAMs+3.3pF cap.
CK3
D8
DQMB6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
-
-
-
-
-
D8
D8
D8
D8
D8
DQM /CS
DQM /CS
D2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
D6
D3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
D7
D0
D0
D0
D0
D0
CKE0
D0 - D8
SERIAL PD
SCL
WP
47K
A0
A1
A2
SDA
D0 - D8
SA0 SA1 SA2
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 3 / 55 )
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776 -BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
-6
-7,-8
-6
-7,-8
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A8
1BANK
x72
0
LVTTL
7.5ns
10ns
5.4ns
6ns
ECC
SPD DATA(hex)
80
08
04
0C
09
01
48
00
01
75
A0
54
60
02
80
08
08
01
8F
04
04
06
01
01
00
0E
00
A0
D0
00
60
70
00
00
17
14
0F
14
17
14
2D
32
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
self refresh(15.625uS)
x8
x8
1
1/2/4/8/Full page
4bank
-6
-7,-8
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
-6
-7
-8
3
2/3
0
0
non-buffered,non-registered
Precharge All,Auto precharge
N/A
10ns
13ns
N/A
6ns
7ns
N/A
24
SDRAM Access form Clock(2nd highest CAS latency)
-6
-7
-8
tAC for CL=2
25
26
27
28
29
30
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
-6
-7,-8
-6
-7,-8
-6
-7,-8
-6
-7,-8
N/A
22.5ns
20ns
15ns
20ns
22.5ns
20ns
45ns
50ns
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 4 / 55 )
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776 -BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
Serial Presence Detect Table II
31
32
33
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
-6
-7,-8
-6
-7,-8
64MByte
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
option
JEDEC2
rev 1.2A
Check sum for -6
Check sum for -7
Check sum for -8
10
15
20
08
10
15
20
08
10
00
02
12
A4
17
57
1CFFFFFFFFFFFFFF
01
02
03
04
4D483853373244414C442D36202020202020
4D483853373244414C442D37202020202020
4D483853373244414C442D38202020202020
34
35
36-61
62
63
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
-6
-7,-8
-6
-7,-8
-6
-7,-8
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH8S72DALD-6
73-90
Manufactures Part Number
MH8S72DALD-7
MH8S72DALD-8
91-92
93-94
95-98
99-125
126
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
-7
-6,-8
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0,2
CL=3,AP,CK0,2
open
rrrr
yyww
ssssssss
00
64
AF
AD
00
127
128+
Intel specification CAS# Latency support
Unused storage locations
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 5 / 55 )
17.Sep.1999
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