HCTS75MS
September 1995
Radiation Hardened
Dual 2-Bit Bistable Transparent Latch
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
Q0 1
D0 1
D1 1
E 2
VCC
D0 2
D1 2
Q1 2
1
2
3
4
5
6
7
8
16 1 Q0
15 1 Q1
14 1 Q1
13 1 E
12
11
GND
2 Q0
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii
≤
5µA at VOL, VOH
10 2 Q0
9
2 Q1
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Q0 1
D0 1
D1 1
E 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1 Q0
1 Q1
1 Q1
1 E
GND
2 Q0
2 Q0
2 Q1
Description
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit
bistable transparent latch. Each of the two latches are controlled
by a separate enable input (E) which are active low. E low latches
the output state.
The HCTS75MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS75MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
VCC
D0 2
D1 2
Q1 2
Functional Diagram
2(6)
D0
13(4)
E
LATCH 0
16(10
D
LE
Q
LE
1(11
Ordering Information
14(8
PART
NUMBER
HCTS75DMSR
TEMPERATURE
RANGE
-55
o
C to +125
o
C
-55
o
C
+125
o
C
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
PACKAGE
16 Lead SBDIP
3(7)
D1
5
12
VCC
GND
LE
D
LE
15(9
Q
LATCH 1
HCTS75KMSR
to
16 Lead Ceramic
Flatpack
16 Lead SBDIP
TRUTH TABLE
INPUTS
D
E
H
H
L
Q
L
H
Q0
OUTPUTS
Q
H
L
Q0
HCTS75D/
Sample
HCTS75K/
Sample
HCTS75HMSR
+25
o
C
+25
o
C
+25
o
C
Sample
16 Lead Ceramic
Flatpack
Die
L
H
Die
X
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
470
518625
3189.1
Specifications HCTS75MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output.
. . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265
o
C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance
θ
JA
θ
JC
o
C/W
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73
24
o
C/W
o
C/W
Ceramic Flatpack Package . . . . . . . . . . . 114
29
o
C/W
Maximum Package Power Dissipation at +125
o
C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/
o
C
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
1
2, 3
Output Current
(Sink)
IOL
VCC = VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
1
2, 3
Output Current
(Source)
IOH
VCC = VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
VCC = 5.5V, VIH = 2.75V,
VIL = 0.8V, IOL = 50µA
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, IOL = 50µA
Output Voltage High
VOH
VCC = 5.5V, VIH = 2.75V,
VIL = 0.8V, IOH = -50µA
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, IOH = -50µA
Input Leakage
Current
IIN
VCC = 5.5V, VIN = VCC or
GND
1
2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C,
-55
o
C
MIN
-
-
4.8
4.0
-4.8
-4.0
-
MAX
20
400
-
-
-
-
0.1
UNITS
µA
µA
mA
mA
mA
mA
V
PARAMETER
Quiescent Current
SYMBOL
ICC
(NOTE 1)
CONDITIONS
VCC = 5.5V,
VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
-
0.1
V
1, 2, 3
VCC -0.1
-
V
1, 2, 3
VCC -0.1
-
V
1
2, 3
-0.5
-5.0
-
+0.5
+5.0
-
µA
µA
V
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
7, 8A, 8B
NOTES:
1. All voltages referenced to device GND.
2. For functional tests VO
≥
4.0V is recognized as a logic “1”, and VO
≤
0.5V is recognized as a logic “0”.
Spec Number
471
518625
Specifications HCTS75MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MAX
19
24
27
35
23
29
19
22
21
25
20
23
24
29
28
34
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
Propagation Delay
D to Q
SYMBOL
TPLH
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
TPHL
Propagation Delay
D to Q
TPLH
TPHL
Propagation Delay
E to Q
TPLH
TPHL
Propagation Delay
E to Q
TPLH
TPHL
NOTES:
1. All voltages referenced to device GND.
2. Measurements made with RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
Input Capacitance
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, f = 1MHz
NOTES
1
1
CIN
VCC = 5.0V, f = 1MHz
1
1
Pulse Width Time
TW
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
1
1
1
1
1
1
1
1
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
-
-
-
-
-
-
-
-
-
-
MAX
36
51
10
10
16
24
12
18
12
18
15
22
UNITS
pF
pF
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
Setup Time
TSU
Hold Time
TH
Output Transition
Time
NOTE:
TTHL,
TTLH
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
472
518625
Specifications HCTS75MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
PARAMETERS
Supply Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
SYMBOL
ICC
IOL
(NOTE 1)
CONDITIONS
VCC = 5.5V, VIN = VCC or GND
VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0V
TEMPERATURE
+25
o
C
+25
o
C
MIN
-
4.0
MAX
0.4
-
UNITS
mA
mA
IOH
VCC = VIH = 4.5V, VOUT = VCC - 0.4V,
VIL = 0V
VCC = 5.5V, VIH = 2.75V, VIL = 0.8V,
IOL = 50µA
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
IOL = 50µA
+25
o
C
-4.0
-
mA
VOL
+25
o
C
-
0.1
V
+25
o
C
-
0.1
V
Output Voltage High
VOH
VCC = 5.5V, VIH = 2.75V, VIL = 0.8V,
IOH = -50µA
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
IOH = -50µA
+25
o
C
VCC
-0.1
VCC
-0.1
-5
-
V
+25
o
C
-
V
Input Leakage
Current
Noise Immunity
Functional Test
Propagation Delay
D to Q
IIN
VCC = 5.5V, VIN = VCC or GND
+25
o
C
+5
µA
FN
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
(Note 3)
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25
o
C
-
-
TPHL
TPLH
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
2
2
2
2
2
2
2
2
35
24
22
29
23
25
34
29
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay
D to Q
TPHL
TPLH
Propagation Delay
E to Q
TPHL
TPLH
Propagation Delay
E to Q
TPHL
TPLH
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO
≥
4.0V is recognized as a logic “1”, and VO
≤
0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE DELTA PARAMETERS (+25
o
C)
GROUP B
SUBGROUP
5
5
PARAMETER
ICC
IOL/IOH
DELTA LIMIT
±6µA
-15% of 0 Hour
Spec Number
473
518625
Specifications HCTS75MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
Interim Test
I
(Postburn-In)
Interim Test
II
(Postburn-In)
PDA
Interim Test
III
(Postburn-In)
PDA
Final Test
Group A (Note 1)
Group B
Subgroup B-5
Subgroup B-6
Group D
NOTES:
1. Alternate group A inspection in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
Sample/5005
Sample/5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 7, 9
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
ICC, IOL/H
READ AND RECORD
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TEST
METHOD
5005
PRE RAD
1, 7, 9
POST RAD
Table 4
READ AND RECORD
PRE RAD
1, 9
POST RAD
Table 4 (Note 1)
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V
±
0.5V
VCC = 6V
±
0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
1, 8, 9, 10, 11, 14, 15, 16
2, 3, 4, 6, 7, 12, 13
-
5
-
-
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
1, 8, 9, 10, 11, 14, 15, 16
12
-
2, 3, 4, 5, 6, 7, 13
-
-
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ
±
5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ
±
5% for dynamic burn-in
12
1, 8, 9, 10, 11, 14, 15, 16
5
4, 13
2, 3, 6, 7
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
1, 8, 9, 14, 15, 16
GROUND
12
VCC = 5V
±
0.5V
2, 3, 4, 5, 6, 7, 10, 11, 13
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ
±
5% for irradiation testing. Group
E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
474
518625
嵌入式系统
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