HCTS160MS
September 1995
Radiation Hardened
Synchronous Counter
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
Features
•
•
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•
•
•
•
•
•
•
•
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3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset: >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
-Standard Outputs 10 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
-VIL = 0.8V Max
-VIH = VCC/2 Min
Input Current Levels Ii
≤
5µA @ VOL, VOH
•
Description
The Intersil HCTS160MS is a Radiation Hardened high speed
presettable BCD decade synchronous counter that features an
asynchronous reset and look-ahead carry logic. Counting and
parallel presetting are accomplished synchronously with the low-
to-high transition of the clock. A low level on the synchronous
parallel enable input, SPE, disables counting and allows data at
the preset inputs, P0 - P3, to be loaded into the counter. The
counter is reset by a low on the master reset input, MR. Two count
enables, PE and TE are provided for n-bit cascading. TE also
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to
enable the next cascaded stage to count.
The HCTS160MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS160MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
MR
CP
P0
P1
P2
P3
PE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
Ordering Information
PART NUMBER
HCTS160DMSR
HCTS160KMSR
HCTS160D/Sample
HCTS160K/Sample
HCTS160HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
DB NA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
File Number
560
518611
2484.2
HCTS160MS
Functional Block Diagram
P0
3
P1
4
P2
5
P3
6
SPE
MR
Q3 Q0 Q3 Q0
CP
MR
D0
T0
Q0
CP Q0
P
MR
D1
T1
CP
Q1
P
MR
D2
T2
CP
Q2
P
MR
D3
T3
Q3
CP Q0
P
Q3 Q3
Q2 Q3 Q0 Q1
Q1
Q0 Q2 Q0 Q3
PE
TE
GND
8
VCC
16
Q0
14
TC
15
Q1
13
Q0
12
Q1
11
TRUTH TABLE
INPUTS
OPERATING MODE
Reset (Clear)
Parallel Load
MR
L
H
H
Count
Inhibit
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
q = Lower case letterindicate the state of the referenced output prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
NOTES:
1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160)
2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation
3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation
X
X
CP
X
PE
X
X
X
h
l (Note 2)
X
TE
X
X
X
h
X
l (Note 2)
SPE
X
l
l
h (Note 3)
h (Note 3)
h (Note 3)
Pn
X
l
h
X
X
X
OUTPUTS
Qn
L
L
H
Count
qn
qn
TC
L
L
(Note 1)
(Note 1)
(Note 1)
L
Spec Number
561
518611
Specifications HCTS160MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output.
. . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265
o
C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance
θ
JA
θ
JC
o
C/W
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73
24
o
C/W
o
C/W
Ceramic Flatpack Package . . . . . . . . . . . 114
29
o
C/W
Maximum Package Power Dissipation at +125
o
C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/
o
C
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .500ns Max
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
1
2, 3
Output Current
(Sink)
IOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
1
2, 3
Output Current
(Source)
IOH
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.8V
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.8V
Output Voltage High
VOH
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.8V
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.8V
Input Leakage
Current
IIN
VCC = 5.5V, VIN = VCC or
GND
1
2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
MIN
-
-
4.8
4.0
-4.8
-4.0
-
MAX
40
750
-
-
-
-
0.1
UNITS
µA
µA
mA
mA
mA
mA
V
PARAMETER
Quiescent Current
SYMBOL
ICC
(NOTE 1)
CONDITIONS
VCC = 5.5V,
VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
0.1
V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
VCC
-0.1
VCC
-0.1
-
-
-
-
V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
V
1
2, 3
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
±0.5
±5.0
-
µA
µA
-
Noise Immunity
Functional Test
NOTES:
FN
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
7, 8A, 8B
1. All voltages referenced to device GND.
2. For functional tests, VO
≥
4.0V is recognized as a logic “1”, and VO
≤
0.5V is recognized as a logic “0”.
Spec Number
562
518611
Specifications HCTS160MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
9
10, 11
TPLH
VCC = 4.5V
9
10, 11
CP to TC
TPHL
VCC = 4.5V
9
10, 11
TPLH
VCC = 4.5V
9
10, 11
TE to TC
TPHL
VCC = 4.5V
9
10, 11
TPLH
VCC = 4.5V
9
10, 11
MR to QN, TC
TPHL
VCC = 4.5V
9
10, 11
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MAX
26
30
23
26
28
32
24
28
27
29
18
20
46
51
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
CP to QN
SYMBOL
TPHL
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, f = 1MHz
NOTES
1
1
Input Capacitance
CIN
VCC = 5.0V,, f = 1MHz
1
1
Output Transition
Time
TTHL
TTLH
VCC = 4.5V
1
1
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C
+25
o
C
+125
o
C
MIN
-
-
-
-
-
-
MAX
104
260
10
10
15
22
UNITS
pF
pF
pF
pF
ns
ns
Spec Number
563
518611
Specifications HCTS160MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K LIMITS
PARAMETER
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
IOL
(NOTES 1, 2)
CONDITIONS
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VCC = 4.5V and 5.5V, VIH = VCC/2,
VIL = 0.8V, IOL = 50µA
VCC = 4.5V and 5.5V, VIH = VCC/2,
VIL = 0.8V, IOH = -50µA
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, (Note 3)
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
TEMPERATURE
+25
o
C
+25
o
C
MIN
-
4.0
MAX
0.75
-
UNITS
mA
mA
Output Current
(Source)
Output Voltage Low
IOH
+25
o
C
-4.0
-
mA
VOL
+25
o
C
-
-0.1
V
Output Voltage High
VOH
+25
o
C
VCC
-0.1
-
-
-
V
Input Leakage Current
Noise Immunity
Functional Test
CP to QN
IIN
FN
+25
o
C
+25
o
C
±5
-
µA
-
TPHL
TPLH
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
2
2
2
2
2
2
2
30
26
32
28
29
20
51
ns
ns
ns
ns
ns
ns
ns
CP to TC
TPHL
TPLH
TE to TC
TPHL
TPLH
MR to QN, TC
NOTES:
TPHL
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO
≥
4.0V is recognized as a logic “1”, and VO
≤
0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25
o
C)
GROUP B
SUBGROUP
5
5
PARAMETER
ICC
IOL/IOH
DELTA LIMIT
12µA
-15% of 0 Hour
Spec Number
564
518611
NXP MCU
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