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HCTS10KMSR

产品描述HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDFP14
产品类别半导体    逻辑   
文件大小151KB,共9页
制造商Intersil ( Renesas )
官网地址http://www.intersil.com/cda/home/
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HCTS10KMSR概述

HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDFP14

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HCTS10MS
September 1995
Radiation Hardened
Triple 3-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
- LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii
5µA at VOL, VOH
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
C1
Y1
C3
B3
A3
Y3
Description
The Intersil HCTS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
The HCTS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS10MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Functional Diagram
An
(1, 3, 9)
Bn
Yn
(6, 8, 12)
Ordering Information
PART
NUMBER
HCTS10DMSR
TEMPERATURE
RANGE
-55
o
C to +125
o
C
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
PACKAGE
(2, 4, 10)
Cn
(5, 11, 13)
TRUTH TABLE
14 Lead SBDIP
INPUTS
An
14 Lead Ceramic
Flatpack
14 Lead SBDIP
L
L
L
L
Bn
L
L
H
H
L
L
H
H
Cn
L
H
L
H
L
H
L
H
OUTPUTS
Yn
H
H
H
H
H
H
H
L
HCTS10KMSR
-55
o
C to +125
o
C
HCTS10D/
Sample
HCTS10K/
Sample
HCTS10HMSR
+25
o
C
+25
o
C
Sample
14 Lead Ceramic
Flatpack
Die
H
H
+25
o
C
Die
H
H
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518778
2434.2

HCTS10KMSR相似产品对比

HCTS10KMSR HCTS10D HCTS10DMSR HCTS10K HCTS10MS HCTS10HMSR
描述 HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDFP14 HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14 HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14 HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14 HCT SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14 HCT SERIES, TRIPLE 3-INPUT NAND GATE, UUC14

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