®
0 &9
V.22bis Single Chip Modem
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Set Top Box
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True one chip solution for embedded
systems
Low operating power
~250mW @ 5V with standby and power
down mode available
Designed for +5 volts (+/-10%)
Data speed:
V.22bis – 2400bps
V.22/Bell212 – 1200bps
V.21/Bell103 – 300bps
V.23 – 1200/75bps
(with PAVI turnaround)
Bell202 – 1200bps
Bell202/V23 4-wire operations
International Call Progress support
FCC68, CTR21, JATE, etc.
Worldwide Caller ID capability
DTMF generation and detection
On chip hybrid driver
Blacklisting capability
Line-In-Use and Parallel Pick-Up (911)
detection capability
Manufacturing Self Test capability
Packaging:
32 pin PLCC / 44 pin TQFP
'HVFULSWLRQ
The 73M2901C/5V is a single-chip modem
that combines all the controller (DTE) and
data pump functions necessary to implement
an intelligent V.22bis data modem. This
device is based on TDK Semiconductor’s
implementation of the industry standard 8032
microcontroller core with a proprietary multiply
and accumulate (MAC) coprocessor; Sigma-
Delta A/D and D/A converters; and an analog
front end. The ROM and RAM necessary to
operate the modem are contained in the
device. Additionally, the 73M2901C/5V
provides an on-chip oscillator and Hybrid
driver.
DATA SHEET
%ORFN 'LDJUDP
BDEN
BDEN
1..
.
592MHz
1 0592MHz
11
0
0592MHz
PLL
PLL
PLL
II
/
/
TR//
TR
ROM
ROM
ROM
HY BR D
HY BR
D
HYBRI
I
I
D
AFE
AFE
AFE
XAP
XAP
XAN
XAN
UART
UART
UART
xCLK
xCLK
TS//
TS
XD
XD
XD
XD
TS//
TS
xCLK
xCLK
CD//
CD
SR//
SR
XA
XA
CP U
CP U
CP U
RAM
RAM
RAM
USER II//O
USER
I/
O
US E R O
SR1..
0
SR1
0
SR1..
1
SR1
1
SR2..
0
SR2
0
ELAY//
ELAY
DAA Suppor
r
t
t
DAA Suppor
t
DAA Suppo
II
NG/
NG /
http://www.tdksemiconductor.com
Rev 2 / August 2002
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®
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+DUGZDUH 'HVFULSWLRQ
The 73M2901C/5V is designed for a single
+5 volt supply with low power consumption
(~250mW @ 5 volts). The modem supports
automatic standby idle mode. The modem
will also accept a request to power down
from the DTE via hardware control. No
additional major components are required
to complete the modem core logic. The
modem provides direct firmware LED
support via port pins.
H
ARDWARE FEATURES
♦
♦
♦
♦
♦
♦
A
NALOG LINE
/
HYBRID INTERFACE
The 73M2901C/5V provides a differential
analog output (TXAP and TXAN) and a
single-ended analog input (RXA) with
internal A/D and D/A converters. A driver is
provided for an internal hybrid function.
The internal hybrid driver is capable of
driving an external load matching
impedance and a line-coupling transformer.
If an external hybrid is to be used, the on-
chip hybrid drivers can be reconfigured to
drive a minimum load of 50k
Ω
and thus
reduce the driver’s power consumption.
The hybrid configuration is controlled by the
state of the HBDEN pin. For driving a line-
coupling transformer, HBDEN should be
pulled high. For driving an external hybrid
(load on TXAP and TXAN is 50k
Ω
or
larger), HBDEN should be pulled low.
The 73M2901C/5V provides firmware
control for a hook relay driver (
5(/$<
) as
well as interrupt support for a ring detect
opto-coupler (
5,1*
).
I
NTERRUPT PINS
The external interrupt sources,
'75
and
5,1*
, come from dedicated input pins of
the same name.
'75
informs the 73M2901C/5V that the
host has requested the 73M2901C/5V
perform a specific function. The actual
particulars of that function can be changed
by “AT” commands (described in full in the
TDK 73M2901C User’s Guide).
5,1*
is used to inform the 73M2901C/5V
that the external DAA circuitry has detected
a ring signal.
In addition, sending any character on the
TXD line also generates an internal
interrupt.
Fully self-contained “AT” Command
interpreter and data pump
User pins available
Synchronous serial data I/O available
Asynchronous serial port
On-chip hybrid driver.
Autobaud capability from 300bps to
9600bps
P
OWER SUPPLY
Power is supplied to the 73M2901C/5V via
the VPD and VPA pins. The 73M2901C/5V
is designed for a single 5 volt (+/-10%)
supply and for low power consumption
(~250mW @ 5 volts). Ground Reference is
provided at the VND and VNA pins.
L
OW POWER MODE
The TDK 73M2901C/5V supports a low
power standby mode. If the low power
standby
option
is
enabled
the
73M2901C/5V will go into a power saving
mode when idle. The oscillator will be
running, clocks will be supplied to the
UART, timers and interrupt blocks; but no
clocks will be supplied to the CPU.
Instruction processing and activity on the
internal busses is halted. Normal operation
is resumed when an interruption such as
assertion of
'75
or
5,1*
, any character is
sent to the 73M2901C/5V, or when a reset
occurs.
DATA SHEET
http://www.tdksemiconductor.com
Rev 2 / August 2002
2 / 16
®
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R
ESET
A reset is accomplished by holding the
RESET pin high. To ensure a proper
power-on reset, the reset pin must be held
high for a minimum of 3
µ
s. At power on, the
voltage at VPD, VPA, and RESET must
come up at the same time for a proper
reset. The signals
'&'
,
&76
and
'65
will
be held inactive for 25ms, acknowledging
the reset operation, within a 250ms time
window after the reset triggering event. The
73M2901C/5V is ready for operation after
that 250ms windows and/or after the
signals
'&'
,
&76
and
'65
become
active.
A
SYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
C
RYSTAL OSCILLATOR
The TDK 73M2901C/5V single chip modem
can use an external 11.0592 MHz
reference clock or can generate such a
clock using only a crystal and two
capacitors. If an external clock is used, it
should be applied to OSCIN.
S
PECIFYING A CRYSTAL
The manufacturer of a crystal resonator
verifies its frequency of oscillation in a test
set-up, but to ensure that the same
frequency is obtained in the application, the
circuit conditions must be the same. The
TDK 73M2901C/5V modem requires a
parallel mode (anti-resonant) crystal, the
important specifications of which are as
follows:
Mode:
Parallel (anti-resonant)
Frequency:
11.0592 MHz
Frequency tolerance:
±50 ppm at initial temperature.
Temperature drift:
±50 ppm additional over full Range.
Load capacitance:
18pF or 20pF
ESR:
75
Ω
max.
Drive level:
Less than 1mW.
The serial data interface consists of the
TXD and RXD data paths (LSB shifted in
and out first, respectively); and the TXCLK
and RXCLK serial clock outputs associated
with the data pins;
&76
/
576
flow control;
'&5
,
'65
and
'75
. In synchronous
mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%)
3LQ 'HVFULSWLRQV
DATA SHEET
P
OWER PIN DESCRIPTION
PIN
NAME
VPA
VNA
VPD
VND
32 pin
PLCC
15
21
6, 25, 29
5, 22, 26
44 pin
TQFP
16
22
2, 12, 27,
33
11, 24,
44, 28
TYPE
I
I
I
I
DESCRIPTION
Positive analog voltage (Analog supply)
Negative analog voltage (Analog ground)
Positive digital voltage (Digital supply)
Negative digital voltage (Digital ground)
http://www.tdksemiconductor.com
Rev 2 / August 2002
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®
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TYPE
I
O
O
I
DESCRIPTION
Receive analog data
Transmit Analog-
Transmit Analog+
2w/4w hybrid driver enable pin
0=Driver configure for 50k
Ω
or greater load
(tie to VND)
1=Driver configured for driving line-coupling
transformer (tie to VPD)
Analog Band Gap voltage reference (0.1
µ
F to
VNA). This pin must not be connected to
another external circuitry other than the
decoupling capacitor.
Analog reference voltage (0.1
µ
F to VNA)
A
NALOG INTERFACE PIN DESCRIPTION
PIN
NAME
RXA
TXAN
TXAP
HBDEN
32 pin
PLCC
20
16
17
14
44 pin
TQFP
21
17
18
15
VBG
19
20
O
VREF
18
19
O
D
IGITAL INTERFACE PIN DESCRIPTION
PIN
NAME
RESET
RXCLK
RXD
TXCLK
TXD
USR10
32 pin
PLCC
13
31
30
28
27
12
44 pin
TQFP
9
36
35
31
30
8
TYPE
I
O
O
O
I
I/O
DESCRIPTION
Reset
Receive data synchronous clock
Serial output to DTE
Transmit data synchronous clock
Serial data input from DTE
Programmable I/O port. This pin can
optionally be used to control an external
switch for caller ID operations or external Line
In Use or Parallel Pick Up circuitry.
Programmable I/O port. This pin can
optionally be used to control an external
switch for caller ID operations or external Line
In Use or Parallel Pick Up circuitry.
Request to send
Clear to send
Data set ready
Data carrier detect
Ring indicator
Relay driver output
Programmable I/O port
USR11
11
7
I/O
576
&76
'65
'&'
5,
5(/$<
USR20
10
9
8
7
4
3
1
6
5
4
3
43
40
38
I
O
O
O
O
O
I/O
DATA SHEET
E
XTERNAL INTERRUPTS PIN DESCRIPTIONS
PIN
NAME
5,1*
'75
32 pin
PLCC
2
32
44 pin
TQFP
39
37
TYPE
I
I
DESCRIPTION
External interrupt – Line interface ring
detection circuitry input
External interrupt – DTE DTR signal input
http://www.tdksemiconductor.com
Rev 2 / August 2002
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TYPE
I
O
DESCRIPTION
Crystal input for internal oscillator, also input
for external source
Crystal oscillator output
O
SCILLATOR PIN DESCRIPTION
PIN
NAME
OSCIN
OSCOUT
32 pin
PLCC
24
23
44 pin
TQFP
26
25
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A
BSOLUTE MAXIMUM RATINGS
Operations above maximum rating may permanently damage the device.
PARAMETER
Supply Voltage
Pin Input Voltage
Storage Temperature
R
ECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Oscillator Frequency
Storage Temperature
R
ECEIVER
PARAMETER
Carrier detect On
Carrier detect Off
Carrier Detect
Hysteresis
Receive Level
Idle channel noise
Input impedance
Receive Gain Boost
Maximum Input Level
at RxA
Total Harmonic
Distortion (THD)
CONDITIONS
Tip and Ring
Tip and Ring
Tip and Ring
Tip and Ring
0.2KHz – 4.0KHz
RXA
SFR 96h bit
2(Rxgain)=1
Vref=1.25V
Vref=2.25V
1KHz 450mVpk on
RXA
nd
rd
THD=2 and 3
harmonic
MIN
-48
2
-43
-70
150
17.75
-9
-65
20.75
0.587
1.069
-50
NOM
MAX
-43
UNIT
1
dBm0
1
dBm0
dB
dBm0
dB
k
Ω
dB
Vpk
Vpk
dB
1
RATING
-0.5V to +7.0V
-0.5V to VPD + 0.5V
-55ºC to 150ºC
RATING
+5V (+/-10%)
11.0592MHz +/- 50ppm
-40ºC to 85ºC
DATA SHEET
-70
http://www.tdksemiconductor.com
Rev 2 / August 2002
5 / 16
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