ADVANCE INFORMATION
Am29LV640DU/Am29LV641DU
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— 2.7 to 3.6 volt read, erase, and program operations
s
VersatileI/O (V
IO
) control
— Output voltages generated and input voltages
tolerated on the device is determined by the voltage
on the V
IO
pin
s
High performance
— Access times as fast as 90 ns
s
Manufactured on 0.23 µm process technology
s
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
s
SecSi (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
s
Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
s
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
s
Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
s
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
s
Minimum 1 million erase cycle guarantee per sector
s
Package options
— 48-pin TSOP
— 56-pin SSOP
— 63-ball FBGA
s
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
s
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
s
Ready/Busy# pin (RY/BY#) (FBGA package only)
— Provides a hardware method of detecting program or
erase cycle completion
s
Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array
data
s
WP# pin (TSOP packages only)
— At V
IL
, protects the first or last 32 Kword sector,
regardless of sector protect/unprotect status
— At V
IH
, allows removal of sector protection
— An internal pull up to V
CC
is provided
s
ACC pin
— Accelerates programming time for higher throughput
during system production
s
Program and Erase Performance (V
HH
not applied to
the ACC input pin)
— Word program time: 11 µs typical
— Sector erase time: 0.7 s typical for each 32 Kword
sector
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
22366
Rev:
A
Amendment/+6
Issue Date:
September 28, 1999
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0
Volt (2.7 V to 3.6 V) single power supply flash memory
devices organized as 4,194,304 words. Data appears
on DQ0-DQ15. The device is designed to be pro-
grammed in-system with the standard system 3.0 volt
V
CC
supply. A 12.0 volt V
PP
is not required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
The device offers access times of 90 120, and 150 ns.
The device is offered in 48-pin TSOP, 56-pin SSOP,
and 63-ball FBGA packages. To eliminate bus conten-
tion each device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 Volt power
supply
(2.7 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The
VersatileI/O™
(V
IO
) control allows the system to
set the output voltage levels generated by the device,
as well as the input voltages tolerated by the device, to
the same voltage level that is asserted on the V
IO
pin.
This allows the device to operate in 1.8 V, 3 V, or 5 V
system environment as required.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The
SecSi (Secured Silicon) Sector
provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The
Write Protect (WP#)
feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
The
accelerated program (ACC)
feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH
, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
2
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