SUMMIT
MICROELECTRONICS, Inc.
Quad 10-Bit Nonvolatile
FEATURES
l
Four Programmable 10-Bit Nonvolatile DACs
M
INL ±1LSB, DNL ±1LSB, 1024 Steps Each
l
Power on Recall at any Value
l
Parallel or Independent Operation of DACs
l
Excellent Temperature Stability - ±15ppm/
0
C
M
Industrial Temperature range
l
1.25V Precision Voltage Reference
l
I
2
C Serial Bus Interface
l
Very Small QFN package
M
5mm square
APPLICATIONS
l
Laser bias/modulation current adjustment
l
Power supply trimming/margining
l
Potentiometer replacement
SMP9410
Preliminary Information
1 see last page
DACPOT
TM
INTRODUCTION
The SMP9410 is a quad 10 bit (1024 steps) Non Volatile
D-to- A converter or DACPOT
TM
. The device will recall any
analog voltage on power up, making it ideal for high
accuracy and temperature stable calibration purposes and
can operate from a single +2.7V to +5.5V supply. Internal
precision buffers swing rail-to-rail with an input voltage
range from ground to the positive supply.
The part integrates four 10-bit DACs and associated cir-
cuits: an enhanced unity gain operational amplifier output,
a 10-bit volatile data latch, a 10-bit nonvolatile data register,
and I
2
C bus industry standard 2-wire serial interface. The
SMP9410 is available in a very small 5mm square Quad Flat
package with No leads (QFN) for small form factor designs.
Programming of configuration, control and calibration val-
ues by the user can be simplified with the interface adapter
and Windows GUI software obtainable from Summit Micro-
electronics.
FUNCTIONAL BLOCK DIAGRAM
VDD
24
100K
3 plcs
13
VREFH0
NON-
VOLATILE
REGISTER
CONFIGURATION
REGISTER
A0
A1
3
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
19
VOUT0
A2
28
SDA
SCL
CS
4
100K
INTERFACE
& CONTROL
LOGIC
2
14
VREFL0
11
VREFH1
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
5
100K
10-BIT
DAC
17
VOUT1
6
12
VREFL1
SMP9410
1.25VREF
20
9
VREFH2
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
PRECISION
REFERENCE
Note: Pin numbers
are for the QFN.
10-BIT
DAC
16
VOUT2
10
VREFL2
7
VREFH3
V
DD
NON-
VOLATILE
REGISTER
VOLATILE
CONTROL
REGISTER
10-BIT
DAC
15
VOUT3
100K
100K
MUTE#_CH
22
MUTE#
23
8
VREFL3
25
GND
2056 BD
©SUMMIT MICROELECTRONICS, Inc., 2002 • 300 Orchard City Dr., #131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com
Characteristics subject to change without notice
2056 2.0 10/04/02
SMP9410
Preliminary Information
DEVICE OPERATION
INTRODUCTION
The device has four 10-Bit digital to analog converters that
are comprised of a resistor network that converts a digital
input into an equivalent analog output voltage in proportion
to the applied reference voltages. The voltage differential
between each V
REF
L and V
REF
H input pair sets the range
and full-scale output voltage for their respective DAC.
Each DAC has a 10-Bit nonvolatile register that can hold a
‘set-and-forget’ value that can be recalled whenever the
device is powered-on.
Each DAC has a 10-Bit volatile register that holds the
current digital value. The register can be set to any value
by the serial interface; commanded to load the zero scale
value, full scale value or mid-scale value; or can recall a
preset value stored in a nonvolatile register.
The device also has a nonvolatile configuration register that
is accessible over the 2-wire bus. The configuration register
is used to select the device type identifier and the DAC
power-on state.
The device uses the industry standard I
2
C 2-wire serial
protocol. The bus is designed for two-way, two-line serial
communication between different integrated circuits. The
two lines are the SCL (serial clock) and SDA (serial data).
Both lines should be pulled up to the positive supply through
a resistor. The protocol defines devices as being either
Masters or Slaves. The SMP9410 will always be a Slave
because it does not initiate any communications or provide
a clock output.
PIN CONFIGURATION
TOP VIEW
QFN
GND
V
DD
MUTE#
MUTE#_CH
TQFP
NC
NC
NC
NC
NC
NC
GND
VDD
MUTE#
MUTE#_CH
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
NC
NC
A2
NC
8
9
10
11
12
13
14
A1
A0
SDA
SCL
CS
V
REF
H3
1
2
3
4
5
6
7
21
20
19
18
17
16
15
NC
1.25V
REF
V
OUT
0
NC
V
OUT
1
V
OUT
2
V
OUT
3
NC
A2
NC
NC
A1
A0
NC
SDA
SCL
CS
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
1.25VREF
NC
VOUT0
NC
VOUT1
VOUT2
NC
VOUT3
NC
NC
28
27
26
25
24
23
22
V
REF
L3
V
REF
H2
V
REF
L2
V
REF
H1
V
REF
L1
V
REF
H0
V
REF
L0
VREFH3
VREFL3
VREFH2
VREFL2
VREFH1
VREFL1
VREFH0
VREFL0
NC
NC
NC
NC
13
14
15
16
17
18
19
20
21
22
23
24
2056 PCon-L
2056 PCon-F
2
2056 2.0 10/04/02
SUMMIT MICROELECTRONICS, Inc.
SMP9410
Preliminary Information
PIN DESCRIPTIONS
Pin #
1,18,21,26,27
3,2,28
4
5
6
13,11,9,7
14,12,10, 8
19,17,15,16
20
22
Type Pin N ame
NC
I
I/O
I
I
I
I
O
O
I
NC
A 0, A 1, A 2
SD A
SC L
CS
Pin D escription
Note: Pin numbers are from LPCC.
No C onnect. NC pi ns are not connected
The address i nputs for the seri al i nterface logi c. Setti ng them hi gh or low
wi ll determi ne the devi ce’ s bus address that i s contai ned wi thi n the seri al
bus data stream. These pi ns have i nternal 100K9 pull-up resi stors to V
DD
The bi di recti onal pi n used to transfer data i n and out of the devi ce.
The seri al i nterface clock. It i s used to clock the data i n and out. Thi s pi n
has an i nternal 100K
9
pull-up resi stor to V
DD
C hi p Select i nput (VIH = selected) Thi s pi n has an i nternal 100KK
9
pull-up
resi stor to V
DD
V
REF
H0, V
REF
H1, The hi gher of the voltage reference i nputs. V
REF
H must be equal to or less
V
REF
H2, V
REF
H3 than V
DD
and greater than V
REF
L.
V
REF
L0, V
REF
L1, The lower of the voltage reference i nputs. V
REF
L must be equal to or greater
V
REF
L2, V
REF
L3 than ground and less than V
REF
H.
V
OUT
0, V
OUT
1,
V
OUT
2, V
OUT
3
1.25V
REF
MUTE#_C H
The voltage output of the D AC s. It i s buffered by a uni ty-gai n follower that
can slew up to 1V/µs.
A 1.25V output reference voltage.
The MUTE#_C Hoi ce i nput sets the V
OUT
levels when MUTE# i s asserted low
(MUTE_C H# hi gh = V
REF
H, MUTE_C H# low = V
REF
L). Thi s pi n has an
i nternal 100K9 pull-up resi stor to V
DD
Forces the VOUT levels to be equal to ei ther the VREFH or VREFL level,
accordi ng to the value of MUTE#_C H (VIL = mute). Thi s pi n has an i nternal
100K
9
pull-up resi stor to V
DD
Power supply i nput.
Power supply return.
23
24
25
I
PWR
PWR
MUTE#
V
DD
GND
SUMMIT MICROELECTRONICS, Inc.
2056 2.0 10/04/02
3
SMP9410
Preliminary Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......................... –55°C to 125°C
Storage Temperature .............................. –65°C to 150°C
Terminal Voltage with Respect to GND:
V
DD
................................ –0.3V to 6.0V
All Others ....................... –0.3V to 6.0V
Output Short Circuit Current……………….……….100mA
Lead Solder Temperature (10 secs).....................300 °C
Junction Temperature.........................................150°C
ESD Rating per JEDEC……………………..………..2000V
Latch-Up testing per JEDEC……………..…......+/- 100mA
Note * - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature ........................................... –40°C to 85°C
Voltage .................................................... 2.7V to 5.5V
Package Thermal Resistance
GJ
A
GJ
C
48 Pin TQFP = 80°C/W, 28 Pin QFN= 80°C/W
48 Pin TQFP = 40°C/W, 28 Pin QFN= 32°C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
RELIABILITY CHARACTERISTICS
Data Retention………………………..……..…..100 Years
Endurance………………………...……….100,000 Cycles
DC OPERATING CHARACTERISTICS
(Over
Recommended Operating Conditions; Voltages are relative to GND)
Symbol
Power
Power supply current
NV write V
DD
= 5.5V
NV write V
DD
= 2.7V
V
DD
= 5.5V; Excluding current
through DACs
V
DD
= 2.7V; Excluding current
through DACs
V
DD
= 5.5V; Total current
including DACs
V
DD
= 2.7V; Total current
including DACs
2.7
0.7
×
V
DD
0.3
×
V
DD
I
OL
= 3mA
V
IN
= 0 to V
DD
V
OUT
powered down in high
impedance mode
Number of NV store operations
NV data retention
1
×
10
6
100
100
10
0.4
3
3
1
1
1
1
5.5
mA
mA
mA
mA
mA
mA
V
V
V
V
µA
µA
NV stores
Years
2056 Elect TableA
Parameter
Condition
Min.
Typ.
Max.
Units
I
DD
Standby or quiescent
Power down
V
DD
V
IH
V
IL
V
OL
I
LI
I
LO
W
END
t
DR
4
Supply voltage
SDA, SCL, CS, MUTE#,
MUTE#_CH, A0, A1, A2
SDA
Input leakage
Output leakage
Write endurance
Data retention
2056 2.0 10/04/02
SUMMIT MICROELECTRONICS, Inc.
SMP9410
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over
Recommended Operating Conditions; Voltages are relative to GND)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Static Performance
N
INL
DNL
VZSE
VFS
TCV
Resolution
Relative Accuracy
Differential nonlinearity
Zero scale error
Full scale voltage
Full scale temperature
coefficient
Offset error
Gain error
Matching Performance
Linearity matching error
Analog Output
I
OUT
LDREG
C
L
BW
THD
Output current@Half Scale
Load regulation @ halfscale
Capacitive load
Dynamic Characteristics
–3dB bandwidth
Total harmonic distortion
Channel-to-channel isolation
Digital cross-talk
Reference Voltages
V
REF
H
V
REF
L
1.25V
REF
V
REF
H > V
REF
L
V
REF
L < V
REF
H
GND
1.2
1.25
1.3
V
DD
V
V
V
R = 10k
Ω
VA = 1V
RMS
, f = 1kHz
f = 1kHz, V
IN
= 100mV
PP
on V
REF
H
100
0.08
–60
–60
kHz
%
dB
dB
Data = 200
HEX
,
∆V
OUT
= ±3LSB,
V
REF
H
X
=V
DD
=5V
Data = 200
HEX
, RL = 1k
Ω
to
∞
No oscillation
-0.25
1
500
+0.25
3
mA
LSB
pF
±1
LSB
–0.2
–0.5
V
REF
H = 5V, V
REF
L = 0V
V
REF
H = 5V, V
REF
L = 0V
Guaranteed monotonic
Data = 000
HEX
Data = 3FF
HEX
±15
+0.2
+0.5
10
–2
–1
0
±1
±0.5
2
1
15
V
REF
H
–1LSB
Bits
LSB
LSB
mV
V
ppm
%VFS
%
2056 Elect TableB
SUMMIT MICROELECTRONICS, Inc.
2056 2.0 10/04/02
5
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