74HC393; 74HCT393
Dual 4-bit binary ripple counter
Rev. 6 — 3 December 2015
Product data sheet
1. General description
The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter
features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4
buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW
transition of nCP. A HIGH on nMR clears the counter stages and forces the outputs LOW,
independent of the state of nCP. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC393: CMOS level
For 74HCT393: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Two 4-bit binary counters with individual clocks
Divide by any binary module up to 28 in one package
Two master resets to clear each 4-bit counter individually
3. Ordering information
Table 1.
Ordering information
Temperature range Name
74HC393D
74HCT393D
74HC393DB
74HCT393DB
74HC393PW
74HCT393PW
74HC393BQ
74HCT393BQ
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
SSOP14
plastic shrink small outline package; 14 leads; body width
5.3 mm
plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT337-1
SOT402-1
SOT762-1
40 C
to +125
C
SO14
Description
Version
Type number Package
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
Nexperia
74HC393; 74HCT393
Dual 4-bit binary ripple counter
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
Fig 4.
State diagram
74HC_HCT393
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 3 December 2015
2 of 19
Nexperia
74HC393; 74HCT393
Dual 4-bit binary ripple counter
Fig 5.
Logic diagram (one counter)
5. Pinning information
5.1 Pinning
Fig 6.
Pin configuration SO14
74HC_HCT393
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 3 December 2015
3 of 19
Nexperia
74HC393; 74HCT393
Dual 4-bit binary ripple counter
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 7.
Pin configuration SSOP14 and TSSOP14
Fig 8.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1CP
1MR
1Q0
1Q1
1Q2
1Q3
GND
2Q3
2Q2
2Q1
2Q0
2MR
2CP
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
clock input (HIGH-to-LOW, edge-triggered)
asynchronous master reset input (active HIGH)
flip-flop output
flip-flop output
flip-flop output
flip-flop output
ground (0 V)
flip-flop output
flip-flop output
flip-flop output
flip-flop output
asynchronous master reset input (active HIGH)
clock input (HIGH-to-LOW, edge-triggered)
supply voltage
74HC_HCT393
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 3 December 2015
4 of 19
Nexperia
74HC393; 74HCT393
Dual 4-bit binary ripple counter
6. Functional description
Table 3.
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
[1]
Count sequence for one counter
[1]
Output
nQ0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
nQ1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
nQ2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
nQ3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14, (T)SSOP14 and DHVQFN14
package
[1]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
Min
0.5
-
-
-
-
-
65
-
Max
+7
20
20
25
±50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
[1]
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT393
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 6 — 3 December 2015
5 of 19
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
